Late-write type semiconductor memory device with...

Details Late-write type semiconductor memory device with... Late-write type semiconductor memory device with...

2000-07-12

2001-11-20

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S230020

Reexamination Certificate

active

06320794

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a late-write type semiconductor memory device like a high speed static RAM (hereinafter referred to as SRAM).
2. Description of the Prior Art
A late-write type SRAM is one of a variety of prior arts concerning a synchronous type semiconductor memory device for high speed operations, where a total time required for write data reduces, resulting in an effect of improving margin of a write operation. One such SRAM is disclosed in U.S. Pat. No. 5,717, 653.
The semiconductor memory device delays a write address input from outside for a number of cycles in the course of performing a late-write process to input to an address decoder and to select word line and bit line. After the write address is input and delayed by a number of cycles, the data input signal input from outside is transmitted to a write driver. Then, the write operation is actuated after a number of cycles. In other words, for instance, in a two cycle late-write process of the semiconductor memory device, write data is input to perform the write operation after a write address is input and delayed by two cycles.
In addition, the conventional semiconductor memory device for high speed operation includes other functions like bypass operation as well as late-write operation. If a write command proceeds to a read command for a number of cycles and both of the write address and read address are identical, the semiconductor memory device performs a bypass operation by immediately outputting the previous write data through the data output buffer without going through a normal read operation of memory cells. However, in such devices there have been a number of data output errors in the high speed operation, rather than in the bypass operation. Some of the causes of these problems are described in detail later in this document. Therefore, the aforementioned data output errors make it difficult to reduce in the time interval of cycles in the bypass operation, so that the semiconductor memory device can not perform at high-speed operation. This limits efforts in improving the performance of the whole system.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a late-write type semiconductor memory device to solve the aforementioned problems.
It is another object of the present invention to provide a late-write type static random access memory suitable for high-speed operation by reducing a time interval of cycles in bypass operation.
It is still another object of the present invention to provide a method for preventing data output errors and reducing a time interval of cycles in bypass operation, and a relevant multiplexer circuit for the late-write type semiconductor memory device.
It is further another object of the present invention to provide a static random access memory with a variety of bypass operation functions for smoothly performing two cycle late-write operation at high speed.
In order to accomplish the aforementioned objects of the present invention, there is provided a semiconductor memory device having a multiplexer circuit for selectively outputting data to be bypassed to a data output buffer. The circuit comprises data channels for channeling individual ones of the data signals prior to outputting to the data output buffer. At least one of the data channels includes:
a first switch for transmitting the first data signal in response to a first state of a first bypass control signal associated with the first data channel;
a latch part for latching the data signal output through the first switch of the first data channel; and
a second switch for transmitting the data signal output from the latch part of the first data channel in response to a second state of the first bypass control signal.
In accordance with another object of the present invention, there is provided a method for channeling a single one of a plurality of data signals prior to selectively outputting one of the data signals to a data output buffer of a semiconductor memory device. The method comprises:
transmitting the single data signal in response to a first state of a bypass control signal associated with the single data signal;
latching the transmitted data signal for preventing data transition; and
transmitting the latched data signal in response to a second state of the bypass control signal.
The semiconductor memory device of the present invention thus constructed prevents data output errors and reduces the time interval of cycles in bypass operation.


REFERENCES:
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5717653 (1998-02-01), Suzuki

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