Semiconductor device manufacturing: process – Making regenerative-type switching device – Having structure increasing breakdown voltage
Reexamination Certificate
2002-07-11
2004-01-06
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making regenerative-type switching device
Having structure increasing breakdown voltage
C438S019000, C438S200000, C438S218000
Reexamination Certificate
active
06673657
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a metric for automatic defect classification in semiconductor wafers. More specifically, for a predetermined stage in a semiconductor fabrication process, the present invention relates to a method for automatic defect classification in a die or integrated circuit of semiconductor wafers for estimating the effect of defects on functionality. Furthermore, the present invention's method of classification gives rise to new possible classes, based on the actual damage caused by a specific defect.
BACKGROUND OF THE INVENTION
Numerous methods are known and described in the literature of semiconductor fabrication process testing and quality assurance. Essentially these processes define the calculation of statistical metrics which vaguely correspond to theoretical intersections between, on the one hand, an area measure for defects and the like and, on the other hand, an area measure for the intentionally printed conductive pattern found on a predetermined region of a semiconductor wafer.
There is a need in the art for an improved method of testing and assurance, be it an improved statistical method, or an improved deterministic method, or an improved combination thereof. It should be recalled that another critical aspect of semiconductor testing and assurance relates to the amount of time consumed by such a method. In terms of an in process testing and assurance method, speed is of the essence. Therefore, a reduction of delays in process testing would likewise represent a significant improvement to the art. Furthermore, an improved testing and assurance method that will facilitate reprocessing of defective batches of wafers would also constitute an improvement to the prior art.
There is a further need in the art to classify defects on semiconductor wafer layers or dies in terms of the relationship between the defects and the surrounding conductive patterns, and to classify defects in terms of their effect on production yield. Additionally, there is a need in the art for the classification of defects relating to missing conductive patterns or portions thereof.
The present invention will be described with the requisite particularity based on preferred embodiments. However, those versed in the art will readily appreciate that various modifications and alterations may be carried out without departing from either the spirit or scope, as hereinafter claimed.
In describing the present invention, explanations are presented in light of currently accepted scientific Technological or Process Control theories and models. Such theories and models are subject to changes, both adiabatic and radical. Often these changes occur because representations for fundamental component elements are developed, because new transformations between these elements are conceived, or because new interpretations arise for these elements or for their transformations. Therefore, it is important to note that the present invention relates to specific technological actualization in embodiments. Accordingly, theory or model dependent explanations herein, related to these embodiments, are presented for the purpose of teaching ordinarily skilled artisans how these embodiments may be substantially realized in practice. Alternative or equivalent explanations for these embodiments may neither deny nor alter their realization.
In addition, the following definitions will be useful for understand the invention as described herein:
Kill Index: Generally, the kill index is a descriptor carrying information regarding the estimated kill rate of a defect. A “kill rate” implies a rate, which is an average (i.e. statistical entity)—and statistical decision making is often employed using a kill rate in order to determine the fate of a batch according to an examination and classification of a few constituent members of that batch. Nevertheless, the “Kill Index”, per se, is not a statistical measure. It is a deterministic metric, derived from the topological relationship between the defect and surrounding imprinted pattern objects, that is related to the damage caused by this defect to the specific integrated circuit. “Kill” is used to denote a dysfunctional integrated circuit.
Killer Defect: A defect, which renders a single die (which corresponds to a single integrated circuit) or portions thereof unable to function adequately or reliably.
Pattern blobs: Distinct pattern areas in a wafer layer or die, defined by a continuous border separating them from the background; for example conductive pattern portions in a wafer layer.
Reference Image: A magnified segment of a layer or die of a semiconductor wafer having no defects either relating to faults in the predetermined topology of the pattern or to additional particles.
Defect Image: A magnified segment of a layer or die of a semiconductor wafer having defects either relating to faults in the predetermined topology of the pattern or to additional particles.
Reference Map: A predetermined image mask of the required pattern topology of each layer of a semiconductor wafer.
Reference Rule Set: A protocol relating to definitions of the geometric shapes and sizes of elements of the topology of a layer or die of a semiconductor wafer such as a straight edge, a specific curvature, intersecting angles and specific lengths.
Non-predetermined Portion: Defects in a semiconductor wafer or layer thereof, random with respect to position even if systematic with respect to process.
Also, the following acronyms are referred to in the following description:
ADC: Automatic defect classification.
CDM: Chamfer distance map.
DFP: Defect's footprint.
EDS: Electron dispersion spectroscopy.
FOV: Field of view.
IPDM: Integer pattern dilated map.
ND: Number of dilations.
PBM: Pattern binary map.
PCZSM: Pattern Complement Zoomed Segment Map (ZSM).
RCFR: Reference to class FOV ratio.
SEM: Scanning Electron Microscopy.
ZSM: Zoomed Segment Map.
SUMMARY OF THE INVENTION
In the process of manufacturing semiconductor wafers, quality control and assurance testing of all parameters is needed after each processing step. An important aspect of this testing relates to classification and detection of the presence and location of defects resulting from the previous manufacturing step. Furthermore, it is necessary to determine if such defects will render the currently exposed layer, die or integrated circuit of the wafer, or presumptively a batch of wafers, incapable of functioning adequately and reliably. Defects that result in a batch of wafers being unsatisfactory are termed “killer defects”. This stage-wise testing and defect classification procedure relates to the exposed layer portion of each wafer subsequent to each manufacturing step.
The present invention relates to embodiments of a kill index classification method for prioritizing relational aspects of topological defect intersections, particularly in association with an intermediate analytical testing stage of a multi-stage semiconductor fabrication process. This method includes the steps of
a) locating a region having at least one non-predetermined portion therein;
b) determining a predetermined topology for the region;
c) calculating evaluation parameters based on the at least one non-predetermined portion in relation to the predetermined topology for the region; and
d) assigning a kill index classification using the calculated evaluation parameters.
More specifically, the kill index that is assigned is linked, correlated and related to the damage caused by the defect to the functionality and/or reliability of the underlying integrated circuit.
Simply stated, the method relates to an analysis of the geometrical relationship between a non-predetermined portion, generally referred to as defects, and the surrounding predetermined topology of the conductive semiconductor pattern, to determine the effect of defects on the functionality and reliability of the currently exposed layer, die or integrated circuit of the wafer. Further, in accordance with this geometrical information, a classification of the
Ben-Porath Ariel
Pnueli Ayelet
Applied Materials Inc.
Nelms David
Nguyen Dao H.
Sughrue Mion LLP
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