Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-10-16
2007-10-16
Lamarre, Guy (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000
Reexamination Certificate
active
11015816
ABSTRACT:
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
REFERENCES:
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patent: 5056093 (1991-10-01), Whetsel
patent: 6081885 (2000-06-01), Deao et al.
patent: 6385749 (2002-05-01), Adusumilli et al.
patent: 6829730 (2004-12-01), Nadeau-Dostie et al.
patent: 7047467 (2006-05-01), Khu et al.
patent: 2003/0046622 (2003-03-01), Whetsel
Bassuk Lawrence J.
Brady W. James
Lamarre Guy
Merant Guerrier
Telecky , Jr. Frederick J.
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