JFET structure for integrated circuit and fabrication method

Details JFET structure for integrated circuit and fabrication method JFET structure for integrated circuit and fabrication method

2005-03-01

2005-03-01

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

C438S188000, C438S196000

Reexamination Certificate

active

06861303

ABSTRACT:
Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.

REFERENCES:
patent: 4373253 (1983-02-01), Khadder et al.
patent: 4503603 (1985-03-01), Blossfeld
patent: 5296409 (1994-03-01), Merrill et al.
patent: 5618688 (1997-04-01), Reuss et al.
patent: 5670393 (1997-09-01), Kapoor
patent: 6352887 (2002-03-01), Hutter et al.

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