Inverter, method of manufacturing the same, and logic...

Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor

Reexamination Certificate

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Details

C326S112000

Reexamination Certificate

active

07977978

ABSTRACT:
Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.

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patent: 4942441 (1990-07-01), Konishi et al.
patent: 4994866 (1991-02-01), Awano
patent: 5721516 (1998-02-01), Furuchi
patent: 6586970 (2003-07-01), Jung
patent: 11-135647 (1999-05-01), None
patent: 2006-237624 (2006-09-01), None
patent: 10-1997-0019085 (1997-04-01), None
patent: 10-1997-019085 (1997-04-01), None
patent: 10-1999-0065451 (1999-08-01), None
patent: 10-2001-0048333 (2001-06-01), None

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