Inverse slope isolation and dual surface orientation...

Details Inverse slope isolation and dual surface orientation... Inverse slope isolation and dual surface orientation...

2007-04-30

2009-08-18

Garber, Charles D. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S429000, C438S701000, C257SE21632, C257SE21548

Reexamination Certificate

active

07575968

ABSTRACT:
A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.

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