Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-05-06
2002-12-24
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
06499124
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to IEEE Standard 1149.1 compliant ICs, and more particularly to IEEE Standard 1149.1 compliant PLDs.
BACKGROUND OF THE INVENTION
Programmable Logic Devices (PLDs) are Integrated Circuits (ICs) that are user configurable and capable of implementing digital logic operations. There are several types of PLDs, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). CPLDs typically include several function blocks that are based on the well-known programmable logic array (PLA) architecture, and include a central interconnect matrix to transmit signals between the function blocks. Signals are transmitted into and out of the interconnect matrix through input/output blocks (IOBs). The input/output function of the IOBs, the logic performed by the function blocks and the signal paths implemented by the interconnect matrix are all controlled by configuration data stored in configuration memory of the CPLD. FPGAs include configurable logic blocks (CLBs) arranged in rows and columns, IOBs surrounding the CLBs, and programmable interconnect lines that extend between the rows and columns of CLBs. Each CLB includes look-up tables and other configurable circuitry that is programmable to implement a portion of a larger logic function. Similar to CPLDs, the CLBs, IOBs and interconnect lines of FPGAs are controlled by configuration data stored in a configuration memory of the FPGA.
PLDs have become popular for implementing various logic functions in electronic systems that, in the recent past, were typically implemented by smaller (<100,000 gates) application specific integrated circuits (ASICs). Such functions include glue logic, state machines, data bus logic, digital signal processors and protocol functions. Early PLDs often provided insufficient capacity to implement these functions, so the significant investment of time and money to design, layout and fabricate an ASIC for these functions was justified. However, recent advances in semiconductor and PLD technologies have produced PLDs with the necessary speed and capacity to implement these functions in most applications. Because PLDs are relatively inexpensive and can be programmed in as little as a few hours, the expense associated with the design, layout and fabrication of ASICs has become harder to justify. Further, the reprogrammability of many PLDs makes them even more attractive than ASICs because it is possible to update (reconfigure) PLDs, whereas ASICs must be replaced. As such, there is a trend toward the use of PLDs in place of ASICS in electronic systems.
As the capacity and performance of PLDs continues to increase, so too does the complexity of the configuration data used to configure the PLDs. In many instances, the configuration data is developed and modified over a long period of time, and represents a significant investment to the company that develops the configuration data. To protect the proprietary interests of such companies, a security function is provided on most PLDs that prevents a would-be pirate from simply downloading the configuration data from the PLD, thereby preventing the would-be pirate from replicating or reproducing the circuit design implemented on the PLD. This security function is typically implemented as a programmable bit that is set during PLD configuration.
IEEE Standard 1149.1 defines circuitry that allows test instructions and associated test data to be fed into a compliant IC and, subsequently, allows the results of execution of such instructions to be read out of the compliant IC. All information (i.e., instructions, test data, and test results) is communicated in a serial format via a four pin serial interface (referred to as the Test Access Port, or TAP) that drives a 16-state controller (state machine) formed in each compliant IC device. The four pins control transitions of the state machine that facilitates loading of instructions and data into the compliant IC device to accomplish pre-defined tasks. As set forth in greater detail below, one such task is a special instruction named INTEST. The INTEST instruction allows static (slow-speed) testing of the on-chip system logic, with each test pattern and response being shifted through a series of Boundary-Scan registers located, for example, at the I/O pins of IEEE Standard 1149.1 compliant PLDs.
A problem presented by IEEE Standard 1149.1 compliant PLDs is that the INTEST instruction can be used by potential pirates to thwart the security function of a PLD in order to replicate or reproduce the circuit design implemented on the PLD. This problem is set forth is additional detail below by first describing IEEE Standard 1149.1 circuitry found on compliant PLDs, and then illustrating by example how the INTEST instruction can be used to determine the configuration data stored on the PLD.
Originally, IEEE Standard 1149.1 was developed to test the interconnections and IC device placement on PCBs through connection pins of the PCBs (i.e., without the need for a mechanical probe). Since its establishment, IEEE Standard 1149.1 has been extended to include device self-tests, diagnostics, and functional tests such as the INTEST instruction.
FIG. 1
shows a simplified electronic system provided for the purpose of explaining the basic concepts of Boundary-Scan Test procedures. The simplified electronic system is formed on a PCB
100
and includes a first PLD
110
and a second PLD
120
.
PCB
100
includes normal operation copper traces formed on a board of insulating material that provide signal paths between a PCB connector
101
and PLDs
110
and
120
, and between PLDs
110
and
120
. These normal operation copper traces are used, for example, to transmit configuration signals to PLDs
110
and
120
, and to carry data signals during device operation. In addition to the normal operation copper traces, PCB
100
includes special purpose copper traces for transmitting signals associated with IEEE Standard 1149.1. These special purpose copper traces include a first trace
102
for transmitting test data-in (TDI) signals, a second trace
103
for transmitting test data-out (TDO) signals, a third trace
104
for transmitting test clock (TCK) signals, and a fourth trace
105
for transmitting test mode select (TMS) signals. Data (TDI/TDO) signals are typically transmitted serially through each compliant device of a system. That is, TDI signals are transmitted on first trace
102
to first PLD
110
, and pass through first PLD
110
along a line
144
(
1
). TDO signals are transmitted from PLD
110
and received as TDI signals by second PLD
120
along a linking trace
106
, and pass through second PLD
120
along a line
144
(
2
). Finally, TDO signals are transmitted from PLD
120
to PCB connector
101
on second trace
103
. In contrast to the data signals, each compliant device receives the TCK and TMS signals in a parallel manner.
Each PLD of an electronic system includes IOBs that configure the device terminals (pins) for transmitting signals to or from the PLDs programmable core logic circuitry. As shown in
FIG. 1
, first PLD
110
includes I/O terminals
112
that transmit/receive signals via lines
114
through respective IOBs
116
to/from programmable core logic circuit
118
. Similarly, second PLD
120
includes I/O terminals
122
that transmit/receive signals via lines
124
through IOBs
126
to/from core logic circuit
128
.
Unlike ASICs, the functions performed by both core logic circuit
118
and IOBs
116
of PLD
110
are determined by configuration data loaded after fabrication. That is, function or functions to be performed by the programmable interconnect and logic circuitry associated with a PLD is determined after fabrication. Similarly, the determination of which I/O pins will be used for input operations, and which I/O pins will be used for output operations is made after fabrication. As described in additional detail below, this flexible pin usage requires each IOB
116
to include programmable circuitry capable of performing both
Bever, Esq. Patrick T.
Ton David
Xilinx , Inc.
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