Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2008-08-26
2011-11-08
Cleary, Thomas J (Department: 2111)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S501000, C713S503000, C327S144000, C327S152000
Reexamination Certificate
active
08055930
ABSTRACT:
An integrated circuit device may include a main clock signal input pad configured to receive a main clock signal having a main clock frequency, a high speed clock signal input pad configured to receive a high speed clock signal having a high speed clock frequency greater than the main clock frequency, a frequency divider, and a phase controller. The frequency divider may be configured to generate a plurality of preliminary internal clock signals responsive to the high speed clock signal wherein each of the preliminary internal clock signals has the same main clock frequency and a different phase. The phase controller may be configured to select one of the preliminary internal clock signals having a phase most closely matched with a phase of the main clock signal, and to translate the preliminary internal clock signals to internal clock signals so that the preliminary internal clock signal having the phase most closely matched with the phase of the main clock signal is translated as a primary internal clock signal, so that the internal clock signals have the main clock frequency. Related methods, systems, and devices are also discussed.
REFERENCES:
patent: 4242741 (1980-12-01), Parrish
patent: 5485490 (1996-01-01), Leung et al.
patent: 6003118 (1999-12-01), Chen
patent: 6078514 (2000-06-01), Takemae et al.
patent: 6201442 (2001-03-01), James et al.
patent: 6327217 (2001-12-01), Chung
patent: 6411161 (2002-06-01), Yamamoto
patent: 6728162 (2004-04-01), Lee et al.
patent: 6792003 (2004-09-01), Potluri et al.
patent: 6909643 (2005-06-01), Kwean
patent: 7391255 (2008-06-01), Matsuzaki
patent: 7778097 (2010-08-01), Chung et al.
patent: 2002/0001360 (2002-01-01), Park et al.
patent: 2002/0093871 (2002-07-01), Kwak
patent: 2002/0174373 (2002-11-01), Chang
patent: 2003/0128597 (2003-07-01), Jun et al.
patent: 2005/0052210 (2005-03-01), Johnson
patent: 2005/0240718 (2005-10-01), Chung et al.
patent: 2006/0017479 (2006-01-01), Kim
patent: 2007/0002644 (2007-01-01), Kang
patent: 2007/0057714 (2007-03-01), Holzle
patent: 2007/0064776 (2007-03-01), Feller et al.
patent: 2007/0146375 (2007-06-01), Kang
patent: 2008/0089167 (2008-04-01), Dono
patent: 2008/0126566 (2008-05-01), Baumgartner et al.
patent: 2008/0143404 (2008-06-01), Shim
patent: 2009/0100285 (2009-04-01), Bae et al.
patent: 2010/0090732 (2010-04-01), Lee et al.
patent: H8-287199 (1996-11-01), None
patent: 2002-352583 (2002-12-01), None
patent: 10-1999-0049424 (1999-07-01), None
patent: 2000-0009138 (2000-02-01), None
patent: 1020020086197 (2002-11-01), None
patent: 1020040095916 (2004-11-01), None
patent: 1020070002803 (2007-01-01), None
JEDEC Standard, DDR2 SDRAM Specification, JESD79-2B, Revision of JESD79-2A, JEDEC Solid State Technology Association, Jan. 2005, pp. 1-103.
Preliminary publication of JEDEC Semiconductor Memory Standard, GDDR4 SGRAM Specification, Feb. 2006, pp. 4-76.
Menolfi et al. “A 16Gb/s Source-Series Terminated Tranmitter in 65nm SOI”, IBM Research GmbH, Zurich Research Laboratory, Ruschlikon, Switzerland, IEEE International Solid-State Circuits Conference 2007, 24 pages.
Bae Seung-jun
Chung Dae-hyun
Kim Jin-Gook
Park Kwang-il
Cleary Thomas J
Myers Bigel Sibley & Sajovec P.A.
Samsung Electronics Co,. Ltd.
LandOfFree
Internal clock signal generating circuits including... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Internal clock signal generating circuits including..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Internal clock signal generating circuits including... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4307957