Internal clock generating circuitry having testing function

Details Internal clock generating circuitry having testing function Internal clock generating circuitry having testing function

2000-04-20

2003-03-11

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C327S159000

Reexamination Certificate

active

06532560

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to internal clock generating circuitry provided with a phase locked loop or PLL built therein for testing an integrated circuit that can operate with a high-speed clock, for supplying an internal clock to the integrated circuit.
2. Description of the Prior Art
Referring next to
FIG. 17
, a schematic circuit diagram is illustrated showing the structure of prior art internal clock generating circuitry having a PLL built therein and a testing function. In the figure, reference numeral
101
denotes a phase comparator for comparing the phases of two input voltages with each other and for generating a voltage VCNT corresponding to the phase difference, numeral
102
denotes a VCO for generating a clock signal having a frequency corresponding to the output voltage VCNT from the phase comparator
101
, numeral
103
denotes a normal clock generating circuit for generating a plurality of normal clock signals from the clock signal, as an original signal applied thereto, from the VCO
102
and for furnishing a feedback signal to the phase comparator
101
, numeral
104
denotes a selector for switching between the plurality of normal clock signals from the normal clock generating circuit
103
and a plurality of test clock signals described below, numeral
105
denotes a voltage controlled delay circuit for generating a clock signal while controlling a delay to be provided for the clock signal according to a control voltage applied thereto, numeral
106
denotes a test clock generating circuit for generating the plurality of test clock signals from the clock signal, as an original signal applied thereto, from the voltage controlled delay circuit
105
, numeral
107
denotes an inverter, and numeral
108
denotes a tristate gate having an inverting function. The VCO
102
generates a clock signal whose frequency is adjusted according to the voltage VCNT from the phase comparator
101
so that the phase difference between the phases of the two input clock signals applied to the phase comparator
101
becomes small. In addition, reference strings Xin and Xout denote input terminals to which signals are applied from outside the internal clock generating circuitry, and reference character A denotes a control signal applied in common to both the selector
104
and the tristate gate
103
.
Referring next to
FIG. 18
, a schematic circuit diagram is illustrated showing the transistor-level structure of the VCO
102
. Each of a plurality of transistor groups
110
a
to
110
e
, each of which is surrounded by a dashed line in the figure, constitutes an inverter. Changing the control voltage VCNT can control a current flowing through each of the plurality of transistor groups that constitutes each of the plurality of inverters
110
a
to
110
e
, thus delaying the transmission of a signal between any two adjacent inverters. In
FIG. 18
, reference characters a, b, c, d, and e denote output signals from the plurality of inverters, respectively.
FIG. 19
is a schematic circuit diagram showing the transistor-level structure of the voltage controlled delay circuit
105
. As can be seen from the figure, the voltage controlled delay circuit
105
can be constructed by connecting two VCOs, as shown in
FIG. 18
, in each of which the loop is, however, opened, so that a plurality of inverters
111
a
to
111
j
are connected in series. Even in this circuit, changing the control voltage VCNT can control a current flowing through each of the plurality of transistor groups that constitutes each of the plurality of inverters
111
a
to
111
j
, thus delaying a clock signal applied to the input terminal Xin by a time delay corresponding to the control voltage while the clock signal travels between any two adjacent inverters.
Referring next to
FIG. 20
, an example is illustrated of the normal clock generating circuit that generates a plurality of normal clock signals based on the clock signal from the VCO. In the figure, reference numerals
120
,
121
,
122
, and
123
denote path transistors, numerals
124
,
125
,
126
,
127
,
128
, and
129
denote inverters, numeral
130
denotes a NAND gate, and numerals
131
and
132
denotes AND gates. In addition, reference characters b, c, and d denote the same signals as the output signals b, c, and d from the VCO as shown in
FIG. 18. A
circuit surrounded by a dashed line is a frequency divider for dividing the frequency of a clock signal applied thereto to generate a clock having a frequency one-half times as large as that of the input clock signal. Since the divider is a well known device in this field, the detailed description of the divider will be omitted hereinafter.
Under normal conditions, the control signal A at a given level is applied to both the tristate gate
108
and the selector
104
so that the tristate gate
108
is brought into conduction and the selector
104
selects the plurality of normal clocks
1
to
3
as a plurality of internal clocks
1
to
3
, respectively. As a result, the clock signal applied to the input terminal Xin is furnished, by way of the other input terminal Xout, to the phase comparator
101
. The phase comparator
101
compares the phase of the clock signal applied to the input terminal Xin with that of the clock signal fed back thereto from the normal clock generating circuit
103
, and then generates and furnishes a voltage VCNT corresponding to the phase difference between those clock signals to the VCO
102
. The VCO
102
oscillates according to the voltage VCNT to supply an original clock signal to the normal clock generating circuit
103
to allow the normal clock generating circuit to generate the plurality of normal clock signals. The normal clock generating circuit
103
divides the frequency of the input original clock signal to generate the plurality of normal clock signals, and then generates and feeds a clock signal whose frequency is one-quarter of that of the original clock signal back to the phase comparator
101
. In this manner, the normal clock generating circuit
103
generates the plurality of normal clock signals
1
to
3
in cooperation with the phase comparator
101
, and the VCO
102
, which constitute a feedback loop together with the normal clock generating circuit
103
. The selector
104
delivers the plurality of normal clock signals
1
to
3
, as the internal clock signals
1
to
3
.
Next, a description will be made as to the operation of each component of the internal clock generating circuitry under normal conditions.
FIG. 21
is a timing chart showing the waveforms of a plurality of clock signals applied to the circuitry and generated in the circuitry under normal conditions. As shown in
FIG. 18
, the VCO
102
determines a oscillating frequency based on the delays which the plurality of inverters included with the VCO
102
provide according to the voltage VCNT from the phase comparator
101
. The output signals b, c, d, and e from the respective stages of the VCO
102
are delayed with respect to the output signals a, b, c, and d by a given time delay, respectively. In addition, each of the output signals b, c, d, and e is the inverse of each of the output signals a, b, c, and d. When the output signals b, c, and d from the VCO
102
are applied to the signals lines b, c, and d as shown in
FIG. 20
, respectively, a signal ICLK
3
is generated from the output signals b and d. Further, another signal ICLK
1
is generated by dividing the output signal c and another signal ICLK
2
, which is the inverse of ICLK
1
, is generated. The VCO
102
then generates a normal clock signal
1
from ICLK
1
and ICLK
3
, and generates a normal clock signal
2
from ICLK
2
and ICLK
3
. In addition, when the frequency divider surrounded by a dashed line of
FIG. 20
receives the normal clock signal
1
via the signal line c, it generates and furnishes a normal clock signal
3
as ICLK
1
.
Next, a description will be made as to the operation of the internal clock generating circuitry that is placed in test mode.

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