Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1998-12-30
2001-08-21
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S624000, C438S631000, C438S699000, C438S790000
Reexamination Certificate
active
06277764
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of forming an interlayer dielectric layer on metal interconnect lines and an interlayer dielectric layer using the same.
2. Description of the Related Art
In general, as the integration of a semiconductor device in the semiconductor fabrication system increases, the operational speed increases. This is very important in forming metal interconnect lines for transmitting electrical signals. In fabrication processes highly integrated semiconductor device technologies for forming multi-layered interconnections are widely used in forming the metal interconnections thereby increasing the integration and improving the operational speed. Meanwhile, as the integration of the semiconductor device increases, the formed space between the metal interconnects becomes narrower. This in turn results in an unwanted increase in capacitance to be generated between the metal interconnects, and thus the operational speed of the semiconductor device must be lowered.
In many cases, it is very important to form an insulating layer between different metal interconnect lines. In the multi-layered interconnection of a highly integrated semiconductor device, an interlayer dielectric layer, typically an inter-metal dielectric film, must have good planarization to solve problems generated by the “bad step coverage,” which is caused by multi-layered interconnection. Thus, the inter-metal dielectric film must have excellent characteristics for filling any narrow spaces between the metal interconnects. Also, the inter-metal dielectric film must be formed of a low dielectric material having a low dielectric constant to reduce the parasitic capacitance generated by adjacent metal interconnections.
A typical low dielectric material used for the interlayer dielectric layer is hydrogen silsesquioxane (HSQ), a spin on glass (SOG) doped with fluorine and a polymer formed by a spin coating, and SiOF, CF, BN and SiCO formed by a chemical vapor deposition (CVD).
Although low dielectric material such as the above low dielectric material layers formed by spin coating can fill the narrow space between the metal interconnect lines, they have difficulties undergoing chemical mechanical polishing (CMP) processing for planarization of the semiconductor surface. Thin film formed by the CVD method have limited ability to fill the narrow space between the metal interconnects.
SUMMARY OF THE INVENTION
To solve the above problems, it is a first object of the present invention to provide a method of forming an interlayer dielectric layer of a semiconductor device in which the interlayer insulating layer has a multi-layered structure including a first insulating layer formed by spin coating and a second insulating layer formed by high density plasma chemical vapor deposition (CVD) on the first dielectric layer. In this way one can (a) fill a space between metal interconnects and (b) easily perform planarization of the semiconductor surface.
It is a second object of the present invention to provide an interlayer dielectric layer formed by the above method.
According to a method of forming an interlayer dielectric layer of a semiconductor device of the present invention, a semiconductor substrate is formed having metal interconnect lines thereon, a first insulating layer of a low dielectric material is formed on the semiconductor substrate, and then a second insulating layer of a low dielectric material is formed on the first insulating layer.
Preferably, the first insulating layer is a hydrogen silsesquioxane (HSQ) layer formed by a spin coating, and the second insulating layer is a SiOF layer formed by the high density plasma chemical vapor deposition (CVD). The second insulating layer is preferably planarized using a CMP process after it is formed on the first insulating layer.
An interlayer dielectric layer of a semiconductor device formed by the method of the present invention includes: a semiconductor substrate wherein a metal interconnect is formed; a first insulating layer of a low dielectric material formed on the semiconductor substrate preferably by a spin coating; and a second insulating layer of a low dielectric material formed on the first insulating layer preferably by a high density plasma chemical vapor deposition (CVD).
According to the method of forming an interlayer dielectric layer of a semiconductor device of the present invention, the interlayer dielectric layer has a multi-layered structure, that is, a first insulating layer, which has the excellent characteristics of filling the space between the metal interconnects, and a second insulating layer formed on the first insulating layer on which a CMP process can be easily performed. Thus, according to the present invention, the space between the metal interconnect lines can be easily filled and the planarization can be simply performed. Also, the interlayer dielectric layer is formed of a low dielectric material layer, to thereby reduce the parasitic capacitance between the metal interconnect lines.
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Kim Sung-jin
Park Hee-sook
Shin Hong-jae
Goodwin David
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Wilczewski Mary
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