Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2000-06-20
2002-09-03
Sherry, Michael (Department: 2829)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
Reexamination Certificate
active
06444592
ABSTRACT:
DESCRIPTION
1. Field of the Invention
The present invention relates to complementary metal oxide semiconductor (CMOS) devices, and mote particularly to a method of integrating a material having a high-dielectric constant (permittivity), i.e., high-k, into a semiconductor processing scheme such that the deposition of the high-k material does not adversely effect the active device region present in a semiconductor substrate.
2. Background of the Invention
Dielectric materials in high density circuits appear as capacitors in dynamic random access memory (DRAM) applications, gate dielectrics in transistors and as decoupling capacitors. The dielectric materials in these structures are typically silicon dioxide (SiO
2
), silicon nitride (Si
3
N
4
) or any combination thereof. These dielectric materials typically have a relative dielectric constant of 8.0 or below.
As today's generation of circuits become smaller and smaller, the dielectric materials employed therein must be made thinner to satisfy circuit requirements. The use of ultra-thin, conventional relatively low-dielectric constant materials in today's circuits is undesirable since such materials lead to leaky circuits. Thus, it would be beneficial if the dielectric constant of the dielectric material used in such circuits could be increased.
A variety of high-dielectric constant materials such as binary metal oxides including aluminum oxide (Al
2
O
3
), zirconium oxide (ZrO
2
), hafnium oxide (HfO
2
), lanthanum oxide (La
2
O
3
), titanium oxide (TiO
2
), as well as their silicates and aluminates; and perovskite-type oxides including a titanate system material such as barium titanate, strontium titanate, barium strontium titanate (BST), lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate, barium lanthanum titanate, barium zirconium titanate; a niobate or tantalate system material such as lead magnesium niobate, lithium niobate, lithium tantalate, potassium niobate, strontium aluminum tantalate and potassium tantalum niobate; a tungsten-bronze system material such as barium strontium niobate, lead barium niobate, barium titanium niobate; and Bi-layered perovskite system material such as strontium bismuth tantalate, bismuth titanate are known in the art.
Binary metal oxides, perovskite-type oxides and other like high-k materials are typically deposited at temperatures of about 400° C. or more. Very often, oxide deposition followed by high-temperature activation anneals up to 1000° C. will be employed. At such high-temperatures, if deposited directly on silicon, interfacial layers form which may degrade device performance. In addition, grain boundary leakage paths and lowered barrier heights may result which could lead to high-device leakage.
In order to integrate high-k materials into current CMOS processing schemes, an interfacial layer composed of an oxide, oxynitride or nitride is oftentimes formed between the device silicon and the deposited high-k material. The function of the interfacial layer is to:
(i) passivate dangling bonds at the surface of the silicon wafers and form a high-quality interface with a low-density of defects;
(ii) create a barrier against interfacial reactions and diffusion into the channel area of a metal oxide semiconductor field effect transistor (MOSFET);
(iii) separate the high-k material from the silicon surface in order to remove charge/traps in the high-k material from the interface; and
(iv) prevent diffusion of dopants and impurities through a gate dielectric.
Moreover, due to parasitic effect of series capacitance, the thickness of the interfacial layer should be minimal (less than 10 Å) to achieve the total equivalent oxide thickness (EOT) of a gate stack, i.e., interfacial oxide and high-k dielectric, that is less 15 Å.
No prior art method known to the applicants is capable of providing an interfacial oxide, oxynitride or nitride layer satisfying the above mentioned requirements. Thus, there is a great need in the semiconductor industry to provide a method in which an ultra-thin interfacial oxide, oxynitride or nitride layer can be formed between the device silicon and the deposited high-k material that satisfies one or more of the above mentioned requirements.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating an ultra-thin interfacial oxide, oxynitride and/or nitride layer that can be utilized between active device regions present in a semiconductor substrate and a high-k material which satisfies one or more of the requirements mentioned in the background section of this application. That is, the inventive method provides an interfacial oxide, oxynitride and/or nitride layer that (i) passivates dangling bonds at the surface of a semiconductor wafer and forms a high-quality interface with a low-density of defects; (ii) creates a barrier against interfacial reactions and diffusion into the channel area (active device region) of a metal oxide semiconductor field effect transistor (MOSFET); (iii) separates the high-k material from the semiconductor surface in order to remove charge/traps in the high-k material from the interface; and (iv) prevents diffusion of dopants and impurities through a gate dielectric.
Moreover, the inventive method is capable of forming a thin interfacial oxide, oxynitride and/or nitride layer having a thickness of less than 10 Å; therefore reducing the parasitic effect of series capacitance which is typically present in prior art CMOS devices.
Specifically, the inventive method, which achieves all of the above objects and advantages, comprises the steps of:
(a) forming an interfacial layer on an active device region of a semiconductor substrate, said interfacial layer comprising an oxide, oxynitride, nitride or mixtures and multilayers thereof having a thickness of less than 10 Å; and
(b) forming a high-k dielectric material on said interfacial layer, said high-k dielectric material having a dielectric constant, k, of greater than 8.
The above processing steps can be integrated with other well known conventional logic processing steps that are capable of forming transistors, capacitors, decoupling capacitors, BiCMOS devices, and other like devices on the high-k dielectric material.
In the present invention, the term “ultra-thin interfacial layer” is used to describe the oxide, oxynitride and/or nitride layer formed in step (a) above. The ultra-thin interfacial layer is formed in the present invention utilizing a rapid thermal oxidation (RTO), a rapid thermal oxynitridation or a rapid thermal nitridation process at reduced or atmospheric pressure; a remote or direct plasma oxidation or oxynitridation process; a wet chemical oxidation process; an ozone process; or a low-energy oxygen implantation following by a rapid thermal annealing process.
Each of the above-mentioned processing techniques that can be used in forming the ultra-thin interfacial oxide, oxynitride or nitride layer, including variations thereto, will be described in more detail hereinbelow.
REFERENCES:
patent: 3479237 (1969-11-01), Bergh et al.
patent: 3735482 (1973-05-01), Norris et al.
patent: 3766637 (1973-10-01), Norris et al.
patent: 5360769 (1994-11-01), Thakur et al.
patent: 5869405 (1999-02-01), Gonzalez et al.
patent: 5872031 (1999-02-01), Mishra et al.
patent: 5972800 (1999-10-01), Hasegawa
patent: 6025280 (2000-02-01), Brady
patent: 6320238 (2001-11-01), Kizilyalli et al.
Wolf, Silicon Processing for the VLSI Era, vol. 2, pp. 434-435.*
E.M. DaSilva, et al., “Fabrication of Aluminum Oxide Films”, IBM Technical Disclosure Bulletin, vol. 4, No. 6, Dec. 1961.
Ballantine Arne W.
Buchanan Douglas A.
Cartier Eduard A.
Chan Kevin K.
Copel Matthew W.
Pepper Margaret A.
Sherry Michael
LandOfFree
Interfacial oxidation process for high-k gate dielectric... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interfacial oxidation process for high-k gate dielectric..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interfacial oxidation process for high-k gate dielectric... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2856260