Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-27
2004-02-17
Labentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S386000, C438S396000, C438S003000
Reexamination Certificate
active
06693004
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the fabrication of an interfacial barrier layer in devices with a high-K gate dielectric material layer.
BACKGROUND ART
Fabrication of a semiconductor device and an integrated circuit including the same begins with a semiconductor substrate and employs film formation, ion implantation, photolithographic, etching and deposition techniques to form various structural features in or on the semiconductor substrate to attain individual circuit components which are then interconnected to form ultimately an integrated circuit. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) circuits requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
There is a demand for large-scale and ultra large-scale integrated circuits employing high performance metal-oxide-semiconductor (MOS) devices. MOS devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region separating the source/drain regions. Above the channel region is typically a thin gate dielectric material, usually referred to as a gate oxide, and a conductive gate comprising conductive polysilicon or another conductive material. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, and complementary MOS (CMOS) devices employing both p-type and n-type devices are formed on a common substrate. MOS technology offers advantages of significantly reduced power density and dissipation as well as reliability, circuit performance and cost advantages.
The drive towards increased miniaturization and the resultant limits of conventional gate oxide layers have served as an impetus for the development of newer, high dielectric constant (“high-K”) materials as substitutes for conventional silicon dioxide-based gate oxide layers. Since the drain current in a MOS device is inversely proportional to the gate oxide thickness, the gate oxide is typically made as thin as possible commensurate with the material's breakdown field and reliability.
Decreasing the thickness of the gate oxide layer between the gate electrode and the source/drain extension regions together with the relatively high electric field across the gate oxide layer, can undesirably cause charge carriers to tunnel across the gate oxide layer. This renders the transistor “leaky”, degrading its performance. To alleviate this problem, high-k dielectric materials are used as the gate insulator. Herein, a high-K gate oxide may be referred to as a high-K gate dielectric material layer, in order to emphasize that the gate dielectric comprises a high-K dielectric material rather than silicon dioxide.
One problem which has been encountered in integrating high-K dielectric materials into CMOS devices, and other semiconductor devices such as EEPROMs and other flash memory devices, is the undesirable interaction between many high-K dielectric materials and the silicon used in other semiconductor device structures. Of particular concern is the interaction between the polysilicon typically used for the gate electrode and the high-K material used for the high-K gate dielectric material. Such undesirable interactions are not confined to CMOS devices, but may also occur between polysilicon gate structures and high-K dielectric insulation layers in SONOS-type devices such as the MIRRORBIT™ flash memory cell available from Advanced Micro Devices, Inc., Sunnyvale, Calif., and in floating gate flash memory cells.
One of the undesirable interactions which may occur is the oxidation of the silicon or polysilicon material in contact with a high-K gate dielectric material layer by oxidizing species used in forming the high-k dielectric material layer, and by the oxygen in the metal oxides of which most high-K dielectric materials are formed. These interactions either lead to an undesirably thick oxide interface at the silicon-high-K interface, or lead to degradation of the high-K by interaction of the polysilicon gate electrode with the high-K gate dielectric during deposition of the polysilicon.
Hence, it would be highly advantageous to develop a process that would permit the use of optimum materials in the formation of a high-K gate dielectric material, without the problems which result from oxidation of silicon, polysilicon or polysilicon-germanium upon which the high-K dielectric material is deposited or which is deposited on the high-K dielectric material. Accordingly, there exists a need for a process of manufacturing MOS semiconductor devices with a high-K dielectric material layer that improves device performance, while avoiding undesirable interactions between elements such as oxidation of silicon substrates or the degradation of high-K gate dielectric materials during deposition of the polysilicon or polysilicon-germanium gate electrode. In particular, a need remains for a process of forming a high-K dielectric material over a silicon substrate, and for forming a polysilicon gate on a high-K gate dielectric material, while avoiding or minimizing oxidation or interaction of high-K dielectric material with the silicon substrate or the polysilicon or polysilicon-germanium gate electrode.
DISCLOSURE OF INVENTION
In one embodiment, the present invention relates to a process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, including steps of depositing on the silicon substrate a first interfacial barrier layer of aluminum oxide, silicon nitride, silicon oxynitride or mixtures thereof; and depositing on the interfacial barrier layer a layer comprising at least one high-K dielectric material, with the proviso that when the first interfacial barrier layer is silicon nitride, silicon oxynitride or mixtures thereof, the layer comprising at least one high-K dielectric material does not include a metal oxynitride.
In another embodiment, the present invention relates to a process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, comprising depositing on the silicon substrate a first interfacial barrier layer of aluminum oxide; and depositing on the first interfacial barrier layer a layer comprising at least one high-K dielectric material.
In still another embodiment, the present invention relates to a process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, comprising depositing on the silicon substrate a first interfacial barrier layer of silicon nitride, silicon oxynitride or mixtures thereof, depositing on the interfacial barrier layer a layer comprising at least one high-K dielectric material, with the proviso that the layer comprising at least one high-K dielectric material does not include a metal oxynitride.
In one embodiment, following deposition of the layer comprising at least one high-K dielectric material layer, a second interfacial barrier layer is deposited on the layer comprising at least one high-K dielectric material.
Following deposition of the foregoing layers, a polysilicon or polysilicon-germanium gate electrode layer may be deposited thereon. The polysilicon or polysilicon-germanium gate electrode may be deposited on the second interfacial barrier layer deposited on the layer comprising at least one high-K dielectric material.
In another embodiment, the present invention relates to a semiconductor device, comprising a silicon substrate; a first interfacial barrier layer on the silicon substrate, the first interfacial barrier layer comprising aluminum oxide, silicon nitride, silicon oxynitride or a mixture thereof and having a thickness in the range from about 1 ang
En William G.
Halliyal Arvind
Ibok Effiong
Jeon Joong S.
Ngo Minh Van
Advanced Micro Devices , Inc.
Labentritt Michael S.
Renner , Otto, Boisselle & Sklar, LLP
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