Inter-level dielectric planarization approach for a DRAM crown c

Details Inter-level dielectric planarization approach for a DRAM crown c Inter-level dielectric planarization approach for a DRAM crown c

1999-06-25

2000-06-20

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438396, 438397, 257296, 257306, H01L 218242, H01L 2120, H01L 2710

Patent

active

060777389

ABSTRACT:
A process for obtaining global planarization, or a smooth top surface topography, for an insulator layer overlying a semiconductor chip, with DRAM device structures, featuring crown shaped capacitor structures, and with peripheral, non-DRAM devices, has been developed. The process features the use of a thin silicon nitride shape, used as a hard mask, overlying insulator layers in the peripheral, non-DRAM device region, and used to prevent removal of these underlying insulator layers, during a wet etch procedure which is used to expose the vertical features of crown shaped, storage node structures, in the DRAM device region. The prevention of removal of insulator, located overlying the peripheral, non-DRAM device region, allows a subsequent, planarized, overlying insulator layer, to provide the desired smooth top surface topography for the entire semiconductor chip.

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