Integration schemes for fabricating polysilicon gate MOSFET...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S592000, C257S392000, C257S407000, C257S412000, C257SE21623

Reexamination Certificate

active

07435652

ABSTRACT:
Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.

REFERENCES:
patent: 6255698 (2001-07-01), Gardner et al.
patent: 6518106 (2003-02-01), Ngai et al.
patent: 6518154 (2003-02-01), Buynoski et al.
patent: 6586288 (2003-07-01), Kim et al.
patent: 6645818 (2003-11-01), Sing et al.
patent: 6746943 (2004-06-01), Takayanagi et al.
patent: 6794234 (2004-09-01), Polishchuk et al.
patent: 6794281 (2004-09-01), Madhukar et al.
patent: 6828181 (2004-12-01), Chen et al.
patent: 6893924 (2005-05-01), Visokay
patent: 7081656 (2006-07-01), Eppich et al.
patent: 7148548 (2006-12-01), Doczy et al.
patent: 2002/0113294 (2002-08-01), Rhee et al.
patent: 2005/0272191 (2005-12-01), Shah et al.
patent: 2005/0275035 (2005-12-01), Mathew et al.
patent: 2005/0282329 (2005-12-01), Li
patent: 2006/0008968 (2006-01-01), Brask et al.
patent: 2006/0017098 (2006-01-01), Doczy et al.
patent: 2006/0071285 (2006-04-01), Datta et al.
patent: 2007/0272975 (2007-11-01), Schaeffer et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Integration schemes for fabricating polysilicon gate MOSFET... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integration schemes for fabricating polysilicon gate MOSFET..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integration schemes for fabricating polysilicon gate MOSFET... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4020124

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.