Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-05-17
2011-05-17
Sandvik, Ben P (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21119, C257SE21133
Reexamination Certificate
active
07943451
ABSTRACT:
Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a (110) direct silicon bonded (DSB) layer on a (100) substrate, regions in the DSB layer are amorphized and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the (110) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.
REFERENCES:
patent: 7608522 (2009-10-01), Lin et al.
patent: 2008/0188046 (2008-08-01), Hierlemann et al.
Johnson Frank S.
Pinto Angelo
Brady III Wade J.
Garner Jacqueline J.
Kuo W. Wendy
Sandvik Ben P
Telecky , Jr. Frederick J.
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