Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-03-30
2009-06-09
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S592000, C438S655000
Reexamination Certificate
active
07544553
ABSTRACT:
To form a semiconductor device, a silicon (e.g., polysilicon) gate layer is formed over a gate dielectric and a sacrificial layer (preferably titanium nitride) is formed over the silicon gate layer. The silicon gate layer and the sacrificial layer are patterned to form a gate structure. A spacer, such as an oxide sidewall spacer and a nitride sidewall spacer, is formed adjacent the sidewall of the gate structure. The semiconductor body is then doped to form a source region and a drain region that are self-aligned to the spacers. The sacrificial layer can then be removed selectively with respect to the oxide sidewall spacer, the nitride sidewall spacer and the silicon gate. A metal layer (e.g., nickel) is formed over the source region, the drain region and the silicon gate and reacted with these regions to form a silicided source contact, a silicided drain contact and a silicided gate.
REFERENCES:
patent: 5225896 (1993-07-01), Van Roozendaal et al.
patent: 5891784 (1999-04-01), Cheung et al.
patent: 6013569 (2000-01-01), Lur et al.
patent: 6080648 (2000-06-01), Nagashima
patent: 6087271 (2000-07-01), En et al.
patent: 6090653 (2000-07-01), Wu
patent: 6100173 (2000-08-01), Gardner et al.
patent: 6271133 (2001-08-01), Lim et al.
patent: 6287925 (2001-09-01), Yu
patent: 6479166 (2002-11-01), Heuer et al.
patent: 6555453 (2003-04-01), Xiang et al.
patent: 6777759 (2004-08-01), Chau et al.
patent: 6784101 (2004-08-01), Yu et al.
patent: 6787424 (2004-09-01), Yu
patent: 7101776 (2006-09-01), Yoo et al.
patent: 2003/0181028 (2003-09-01), Yeap et al.
patent: 2004/0038435 (2004-02-01), Wieczorek et al.
patent: 2005/0037558 (2005-02-01), Gong et al.
patent: 2006/0172492 (2006-08-01), Froment et al.
patent: 1 463 102 (2004-09-01), None
patent: 1 496 541 (2005-01-01), None
patent: WO 2004/057659 (2004-07-01), None
Culmsee Marcus
Doni Lothar
Wendt Hermann
Infineon - Technologies AG
Slater & Matsil L.L.P.
Trinh Michael
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