Pulse or digital communications – Receivers – Automatic baseline or threshold adjustment
Reexamination Certificate
2006-07-28
2009-10-13
Fan, Chieh M (Department: 2611)
Pulse or digital communications
Receivers
Automatic baseline or threshold adjustment
C376S316000, C455S313000
Reexamination Certificate
active
07602861
ABSTRACT:
A wireless receiver includes a hardware (HW) block, a converter block and a digital signal processor (DSP). The HW block receives a wireless signal having a first DC Offset Component (DCOC), removes a portion of the first DCOC to produce a residual DCOC centered at DC, and generates parameters that estimate the residual DCOC. The converter block is coupled to the HW block and receives the residual DCOC centered at DC and converts it to a residual DCOC centered at IF. The DSP is coupled to the HW block and the converter block and receives the residual DCOC centered at IF from the converter block and the parameters from the HW block, and uses the parameters to eliminate the residual DCOC, and generate a baseband signal that is substantially free of the first DCOC and the residual DCOC.
REFERENCES:
patent: 4887050 (1989-12-01), Borth et al.
patent: 2003/0142234 (2003-07-01), Dent
patent: 2003/0174641 (2003-09-01), Rahman
patent: 2005/0009493 (2005-01-01), Yang et al.
patent: 2007/0253510 (2007-11-01), Danz
Schwartz Daniel B.
Wong Man Shing
Bergere Charles
Fan Chieh M
Freescale Semiconductor Inc.
Nguyen Leon-Viet Q
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