Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-01-05
2001-03-27
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000
Reexamination Certificate
active
06207485
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit manufacturing and more particularly to forming insulated gate field effect transistors.
BACKGROUND OF THE INVENTION
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. Currently, the gate oxide is formed having a substantially uniform thickness. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of second conductivity type (P or N) into a semiconductor substrate of first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide a gate which provides a mask during formation of the source and drain by ion implantation. Thereafter, a drive-in step is applied to repair crystalline damage and to drive-in and activate the implanted dopant.
There is a desire to reduce the dimensions of the IGFET. The impetus for device dimension reduction comes from several interests. One is the desire to increase the number of individual IGFETs that can be placed onto a single silicon chip or die. More IGFETs on a single chip leads to increased functionality. A second desire is to improve performance, and particularly the speed, of the IGFET transistors. Increased speed allows for a greater number of operations to be performed in less time. IGFETs are used in great quantity in computers where the push to obtain higher operation cycle speeds demands faster IGFET performance.
One method to increase the speed of an IGFET is to reduced the length of the conduction channel underneath the gate and dielectric layer regions. However, as IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3 V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3 V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. Several methods have been used in the past to form a graded doping region. One common technique for use with a typical gate having a gate oxide with a uniform thickness, is the formation of a graded doping in both the source region and the drain region. The most common way to form a graded doping region is to form a lightly doped region in the drain with a first ion implant using the sidewalls of a gate as a self-aligning mask. Spacers are then formed on the sidewalls of the gate and a second implant of dopant is made. In other words, the drain is typically formed by two ion implants. The first light implant is self-aligned to the gate, and a second heavy implant is self-aligned to the gate on which sidewall spacers have been formed. The spacers are typically oxides or nitrides. The part of the drain underneath the spacers is more lightly doped than the portion of the drain not shielded by the spacers. This more lightly doped region is referred to as a lightly doped drain (LDD).
The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The purpose of the lighter first dose is to form a lightly doped region of the drain (or Ldd) at the edge near the channel. The second heavier dose forms a low resistivity heavily doped region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. The lightly doped region is not necessary for the source (unless bidirectional current is used), however lightly doped regions are typically formed for both the source and drain to avoid additional processing steps.
As shown above, a threshold point exist where heightened speed and reduced dimensions will lead to IGFET breakdown. Conventional approaches have encountered difficulty trying to reconcile the methods for decreasing the hot carrier effects and the methods for improving performance. Also, it is desirable to achieve improved these sought after results without adding costly processing steps. Thus, it is an objective to uncover newly configured IGFET structures and the methods to produce the same which will increase performance increase and while not compromise the IGFET's longevity or fabrication costs.
Graded-drain regions can be created in IGFETs in a number of ways, including: (1) using phosphorus in place of arsonic as the dopant of the source/drain regions; (2) adding fast diffusing phosphorus to an As-doped drain region, and driving the phosphorus laterally ahead of the arsenic with a high temperature diffusion step to create a double-diffused drain [DDD] structure; and ® pulling the highly doped (n+) drain region away from the gate edge with an “oxide spacer” to create a lightly doped drain (LDD) structure. Each of these methods requires a number of processing steps. Most require two implant steps to form a lightly doped region and a heavily doped region. A method is needed which reduces the number of implant processing steps.
SUMMARY OF THE INVENTION
A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so that the first and second materials are sandwiched between the conductor and the semiconductor substrate. Since the dielectric constants of the two materials are different, the gate acts like a gate having a single dielectric with at least two thicknesses. This is due to the fact that each material has a dielectric constant that is different. One dielectric constant is larger than the other dielectric constant. The higher dielectric constant material is comprised of two spacers at the sidewalls of the gate. A layer of silicon dioxide is positioned on the semiconductor substrate between the spacers. The thickness of the spacers can be adjusted
Fulford H. James
Gardner Mark I.
May Charles E.
Advanced Micro Devices
Jr. Carl Whitehead
Vockrodt Jeff
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