Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-08-12
2004-01-13
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S719000, C134S001100, C134S001200
Reexamination Certificate
active
06677242
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of etching silicon. More specifically, the present invention relates to an integrated silicon etch process including performing photoresist removal and silicon etch steps within the same chamber.
Today's semiconductor chips generally include millions of transistors. Isolation structures are provided between the transistors to prevent short circuit from occurring between adjacent transistors. One commonly used isolation structure is the shallow trench isolation (STI) structure. The STI structure has generally been made using an ex-situ hard mask STI or in-situ photoresist STI approaches.
The ex-situ hard mask approach generally involves forming a pad oxide layer and a silicon nitride layer successively over a silicon substrate. A photoresist layer is formed over the nitride layer and then patterned. The substrate is transferred to a first chamber to remove the exposed portions of the nitride and oxide layers thereunder. The substrate is then transferred to a second chamber to strip the photoresist. Thereafter, the substrate is transferred to a third chamber to etch the exposed portions of the silicon substrate to form trenches which will subsequently be filled with dielectric material, such as SiO
2
, to produce shallow trench isolation structures. Each of the first, second and third chambers being optimized to perform its particular etching operation. One problem with this approach is that it requires at least three different etch chambers which increases the cost of ownership per wafer. In addition, transferring the substrates into and out of these three chambers reduces throughput and may cause particle and/or defect control problems.
Mindful of these disadvantages, the in-situ photoresist approach, which uses one less chamber than the ex-situ hard mask approach, has recently been gaining wider use. This process involves forming a pad oxide layer and a silicon nitride layer successively over a silicon substrate. A photoresist layer is formed over the nitride layer and then patterned. The substrate is transferred to a silicon etch chamber. The exposed portions of the nitride layer and the oxide layer thereunder are etched to expose selected portions of the silicon substrate. Afterwards, within the same chamber, the selected portions of the substrate are etched to form trenches. Then the substrate is transferred to a photoresist stripping chamber, such as the chamber, to strip the patterned photoresist.
Although the in-situ photoresist approach provides improved throughput and better particle/defect control management than the ex-situ hard mask approach, the former approach creates some problems of its own. One problem is that the photoresist becomes difficult to strip if removed after the silicon etch step since the byproducts, e.g., SiO
2
, from silicon etch step are mixed with the remaining photoresist. Another problem is that the in-situ method results in increased profile micro-loading effects over the ex-situ hard mask step. The former generally has variance of 8-10 degrees or more for trenches targeted to have a taper angle of 85 degrees. In comparison, the latter generally produces variance of 3-5 degrees for the targeted structure. The profile micro-loading effect refers to the difference in trench taper angles of the dense areas and those in the iso areas. In addition, the in-situ photoresist approach also produces increased etch-rate micro-loading effect over the ex-situ hard mask approach. The former generally producing the etch rate depth variance of 300 Å or more for trenches etched to a depth of about 3,500 Å. In comparison, the latter has the etch rate depth variance of about 200 Å or less for the substantially same structure. The etch-rate micro loading effect refers to the difference in etch rate depths at the dense and iso areas.
Accordingly, it is desirable to develop a STI approach that can increase throughput and improve particle/defect control without the disadvantages associated with the in-situ photoresist step STI approach.
SUMMARY OF THE INVENTION
The present invention provides an improved method for etching silicon. Embodiments of the invention teaches performing photoresist stripping method and silicon etch steps within the same chamber. The present invention increases the throughput of silicon substrate processing.
According to one embodiment of the present invention, a method for processing a silicon substrate disposed in a substrate process chamber includes transferring the substrate into the substrate process chamber. The substrate having a hard mask formed thereon and a patterned photoresist overlying the hard mask to expose portions of the hard mask. The chamber being the type having a source power system and a bias power system. The method further includes etching the exposed portions of the hard mask to expose portions of the silicon substrate underlying the hard mask. Thereafter, the patterned photoresist is exposed to a first plasma formed from a first process gas to remove the photoresist from the hard mask. Thereafter, the exposed silicon substrate is etched by exposing the substrate to a second plasma formed from a second process gas by applying RF energy from the source power system and biasing the plasma toward the substrate. The substrate is transferred out of the substrate processing chamber.
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Wang et al. “In-Situ SHallow Trench Isolation Etch With Clean Chemistry,” 23rd IEEE/CPMT International Electronics Manufacturing Technology Symposium, pp. 150-154, (1998).
Liu Wei
Mui David
Williams Scott
Yuen Stephen
Applied Materials Inc.
Bach Joseph
Deo Duy-Vu
Norton Nadine G.
Townsend & Townsend & Crew
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