Integrated semiconductor circuit with a dynamic read-write memor

Details Integrated semiconductor circuit with a dynamic read-write memor Integrated semiconductor circuit with a dynamic read-write memor

1983-11-21

1986-07-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365193, G11C 700

Patent

active

046023534

ABSTRACT:
Integrated semiconductor circuit with a dynamic read-write memory having a memory matrix composed of identical memory cells addressable via row and column decoders with respect to the individual memory cells, the addressing of the individual matrix rows being initiated by a row address strobe while the addressing of the individual matrix columns is initiated by a column address strobe, the addressing being such that during read-out, simultaneously, the information contents of at least two of the memory cells intended for data storage is processed and temporarily stored in an interim register, and including, in addition, a shift register exclusively operated by the column address strobe for the serial transmission of the information contents simultaneously obtained from the memory matrix to the data output of the memory, including means for controlling the data output of the memory via the column address strobe so that the information present at the data output of the memory and made available by the shift register is preserved at the data output of the memory after decay of the column address strobe signal causing readout of the information for a defined time span.

REFERENCES:
patent: 4397001 (1983-08-01), Takemae

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