Integrated plasma etch of gate and gate dielectric and low...

Details Integrated plasma etch of gate and gate dielectric and low... Integrated plasma etch of gate and gate dielectric and low...

2002-03-18

2002-09-17

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S689000, C438S694000, C438S761000, C438S785000, C257S310000, C257S410000

Reexamination Certificate

active

06451647

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the formation of a gate stack by an integrated plasma etch of gate and gate dielectric layers. The invention further relates to integration of high-K dielectric materials into existing semiconductor fabrication processes.
BACKGROUND ART
Fabrication of a semiconductor device and an integrated circuit thereof begins with a semiconductor wafer and employs various processes, such as film formation, ion implantation, photolithography, etching and deposition techniques to form various structural features in or on a semiconductor wafer to attain individual circuit components which are then interconnected to ultimately form an integrated semiconductor circuit. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
There is a demand for large-scale and ultra large-scale integration devices employing high performance metal-oxide-semiconductor (MOS) devices. MOS devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region separating the source/drain regions. Above the channel region is typically a thin gate dielectric material, usually referred to as a gate oxide, and a conductive gate comprising conductive polysilicon or another conductive material. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, and complementary MOS (CMOS) devices employing both p-channel and n-channel devices are formed on a common substrate. MOS technology offers advantages of significantly reduced power density and dissipation as well as increased reliability, circuit performance and cost advantages.
The drive towards increased miniaturization and the resultant limits of conventional gate oxide layers have served as an impetus for the development of newer, high dielectric constant (“high-K”) materials as substitutes for conventional silicon dioxide-based gate oxide layers. Since the drain current in a MOS device is inversely proportional to the gate oxide thickness, the gate oxide is typically made as thin as possible commensurate with the material's breakdown potential and reliability.
Decreasing the thickness of the gate oxide layer between the gate electrode and the source/drain extension regions together with the relatively high electric field across the gate oxide layer, can undesirably cause charge carriers to tunnel across the gate oxide layer. This renders the transistor “leaky”, degrading its performance. To alleviate this problem, high-K dielectric materials are used as the gate dielectric. Herein, a high-K gate oxide may be referred to as a high-K gate dielectric material layer, in order to emphasize that the gate dielectric comprises a high-K dielectric material rather than silicon dioxide, which is often referred to simply as “oxide”.
When integrating new materials and/or processes into the fabrication of a semiconductor device, there is a strong need to do so with as little change as possible to existing facilities and equipment and to reduce the number of additional steps required by the new materials and processes. In addition, it is desirable to reduce the number of times a semiconductor wafer is handled or transferred during fabrication. As a result of new materials and/or processes, it is often necessary to address new problems presented by the new materials and/or processes which are to be integrated into existing processes, and it is sometimes possible to combine steps which would otherwise be discrete.
One problem with the addition of high-K dielectric materials to semiconductor devices arises during fabrication. In conventional devices, in which silicon dioxide is applied as a layer on a semiconductor wafer and a portion of the layer forms a gate dielectric, in most processes the portions of the layer not forming the gate dielectric can be allowed to remain on the other surfaces of the wafer. Unlike such silicon dioxide layers, when a layer of high-K dielectric material is applied as a layer and a portion of this layer is to be used as the gate dielectric, the remaining portions of the high-K dielectric material layer may be not wanted or may be deleterious, and so should be removed from the wafer. The removal of such high-K dielectric material has required a separate processing step in a separate apparatus from that used to form the gate structure. In addition, known etch chemistries for polysilicon and high-K dielectric materials are quite different, and require separate steps. It would be advantageous to simplify this process.
Another problem which has been encountered in integrating high-K dielectric materials into processes for fabrication of CMOS devices, is undesirable contamination of process apparatus and semiconductor devices resulting from the introduction of high-K dielectric materials into the fabrication process. Of particular concern in the present case is the possible contamination, from unwanted residual high-K dielectric material remaining after process steps such as polysilicon gate deposition and gate etching, to other semiconductor devices which do not contain high-K dielectric materials or which are sensitive or susceptible to such contamination. For example, during the gate etch steps, sub-microscopic or larger particles of unwanted residual high-K dielectric material may become deposited or may inadvertently remain on the semiconductor wafer. When the high-K containing semiconductor wafer is subsequently processed in an apparatus which also is used in processing a non-high-K-containing semiconductor wafer, the latter wafer may become contaminated with the high-K dielectric material, which may be present as an unwanted residual on the high-K containing wafers. For example, the apparatus may become contaminated with high-K dielectric material from the high-K containing wafer, resulting in contamination of wafers subsequently processed in the same apparatus.
Such undesirable interactions are not confined to CMOS devices. These interactions may also occur between polysilicon control gate and floating gate structures and adjacent high-K dielectric insulation or charge storage layers in SONOS-type devices such as the MIRRORBIT™ flash memory cell available from Advanced Micro Devices, Inc., Sunnyvale, Calif. These interactions may also occur, for example, in floating gate flash memory cells in devices such as EEPROMs and other flash memory devices.
Hence, it would be highly advantageous to develop a process that would permit the integration of high-K materials into existing fabrication apparatus and processes, in which the high-K material could be processed together with high-K-sensitive elements while minimizing contamination of the high-K-sensitive elements with high-K material. It is also advantageous to optimize methodologies of MOS fabrication. Accordingly, there exists a need for a process of fabricating semiconductor devices with a high-K dielectric material layer which reduces the number of process steps and, improves device performance, while avoiding undesirable interactions between unwanted residual high-K dielectric materials remaining on semiconductor wafers containing such high-K dielectric materials and semiconductor wafers which do not include high-K dielectric materials.
DISCLOSURE OF INVENTION
In one embodiment, the present invention relates to a process of fabricating a semiconductor device, including steps of providing a first semiconductor wafer; depositing on the first semiconductor wafer a layer comprising a high-K dielectric material layer; depositing on the layer comprising a high

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