Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-10-22
2002-04-02
Hiteshew, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S693000, C438S697000, C438S700000, C438S760000
Reexamination Certificate
active
06365523
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming patterned planarized aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications. More particularly, the present invention relates to high density plasma chemical vapor deposition (HDP-CVD) methods in conjunction with chemical mechanical polish (CMP) planarizing methods for forming patterned planarized aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronics fabrications are formed from semiconductor substrates within and upon whose surfaces are formed semiconductor integrated circuit devices. The semiconductor integrated circuit devices are connected internally and externally to the semiconductor substrates upon which they are formed through use of patterned conductor layers which are separated by dielectric layers.
As semiconductor integrated circuit microelectronics fabrication integration levels have increased and semiconductor integrated circuit device and patterned conductor layer dimensions have decreased, it has become more prevalent in the art of semiconductor integrated circuit microelectronics fabrication to employ trench isolation methods, such as but not limited to shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods, to form patterned planarized trench isolation regions within isolation trenches within semiconductor substrates in order to separate active regions of the semiconductor substrates within and upon which are formed semiconductor integrated circuit devices.
Such shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are desirable for forming patterned planarized trench isolation regions within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications since shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods typically provide patterned planarized trench isolation regions which are nominally co-planar with the surfaces of adjoining active regions of a semiconductor substrate which they separate. Such nominally co-planar patterned planarized trench isolation regions and adjoining active regions of a semiconductor substrate generally optimize an attenuated depth of focus typically achievable with an advanced photoexposure apparatus employed when forming advanced semiconductor integrated circuit devices and patterned conductor layers within an advanced semiconductor integrated circuit microelectronics fabrication.
Of the methods which may be employed for forming patterned planarized shallow trench isolation (STI) regions within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications, high density plasma chemical vapor deposition (HDP-CVD) methods employed in conjunction with chemical mechanical polish (CMP) planarizing methods have recently received considerable attention. High density plasma chemical vapor deposition (HDP-CVD) methods are typically characterized as, and alternately known as, simultaneous chemical vapor deposition (CVD) and inert gas ion sputter (typically argon ion sputter) methods, where a deposition rate within the chemical vapor deposition (CVD) method exceeds a sputtering rate within the inert gas ion sputtering method.
While high density plasma chemical vapor deposition (HDP-CVD) methods undertaken in conjunction with chemical mechanical polish (CMP) planarizing methods are thus desirable within the art of semiconductor integrated circuit microelectronics fabrication for forming patterned planarized trench isolation regions within isolation trenches within semiconductor substrates employed within advanced semiconductor integrated circuit microelectronics fabrications, patterned planarized trench isolation regions are often not formed entirely without problems within semiconductor integrated circuit microelectronics fabrications while employing high density plasma chemical vapor deposition (HDP-CVD) methods in conjunction with chemical mechanical polish (CMP) planarizing methods. In particular, it is often difficult to form with optimal uniformity and planarity, and with attenuated semiconductor substrate damage, a series of patterned planarized trench isolation regions within a series of isolation trenches separated by a series of mesas of varying width but substantially equivalent height within a semiconductor substrate while employing a high density plasma chemical vapor deposition (HDP-CVD) method in conjunction with a chemical mechanical polish (CMP) planarizing method as is conventional in the art of semiconductor integrated circuit microelectronics fabrication.
It is thus towards the goal of forming within a semiconductor integrated circuit microelectronics fabrication with optimal uniformity and planarity and with attenuated semiconductor substrate damage a series of patterned planarized trench isolation regions within a series of isolation trenches separated by a series of mesas of varying width while employing a high density plasma chemical vapor deposition (HDP-CVD) method in conjunction with a chemical mechanical polish (CMP) planarizing method, that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards providing a method for forming within a microelectronics fabrication which need not necessarily be a semiconductor integrated circuit microelectronics fabrication, with optimal uniformity and planarity and with attenuated microelectronics substrate damage, a series of patterned planarized aperture fill layers within a series of apertures separated by a series of mesas of varying width, while employing a high density plasma chemical vapor deposition (HDP-CVD) method in conjunction with a chemical mechanical polish (CMP) planarizing method.
Various methods have been disclosed in the art of microelectronics fabrication for forming planarized aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications.
For example, Nag et al., in “Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25 &mgr;m Technologies,” IEDM 96, IEEE, pp. 841-44, compares a series of physical and electrical properties for each of several dielectric materials formed employing several corresponding deposition methods which may be employed in conjunction with chemical mechanical polish (CMP) planarizing methods for forming patterned planarized trench isolation regions within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications.
In addition, Avanzino et al., in U.S. Pat. No. 4,954,459, discloses a polishing planarizing method for forming a planarized aperture fill dielectric layer within an aperture, such as but not limited to an isolation trench, within a topographic substrate layer, such as but not limited to a semiconductor substrate, employed within a semiconductor integrated circuit microelectronics fabrication. The method employs a conformal dielectric oxide layer formed over the topographic substrate layer, where upper lying portions of the conformal dielectric oxide layer corresponding with upper lying features of an underlying topography of the topographic substrate layer are selectively etched prior to a polish planarizing of the etched conformal dielectric oxide layer so formed.
Further, Sato, in U.S. Pat. No. 5,182,221, discloses an electron cyclotron resonance chemical vapor deposition (ECR-CVD) method for forming a void free planarized aperture fill layer within an aperture within a topographic substrate layer employed within a microelectronics fabrication, where the void free planarized aperture fill layer is formed without increasing an aspect ratio of the aperture into which is formed the
Chen Ying-Ho
Fu Chu-Yun
Jang Syun-Ming
Ackerman Stephen B.
Brown Charlotte A.
Hiteshew Felisa
Saile George O.
Stanton Stephen G.
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