Integrated dielectric and method

Details Integrated dielectric and method Integrated dielectric and method

1998-05-05

2002-01-01

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S931000, C257S077000

Reexamination Certificate

active

06335238

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains generally to the integration of dielectrics with integrated circuits, and more particularly to reaction barriers between high-k dielectrics and an underlying Group IV semiconductor layer.
BACKGROUND OF THE INVENTION
Semiconductors are widely used in integrated circuits for electronic devices such as computers and televisions. These integrated circuits typically combine many transistors on a single crystal silicon chip to perform complex functions and store data. Semiconductor and electronics manufacturers, as well as end users, desire integrated circuits that can accomplish more functions in less time in a smaller package while consuming less power.
Most semiconductor memories use an array of tiny capacitors to store data. One approach to expanding the capacity of a memory chip is to shrink the area of each capacitor. However, everything else being equal, a smaller area capacitor stores less charge, thereby making it more difficult to integrate into a useful memory device. One approach to shrinking the capacitor area is to change to a storage dielectric material with a higher permittivity. To the best of our knowledge, past efforts to incorporate high permittivity (high-k) materials into integrated circuits have not proven completely satisfactory.
In another, related area, one concern is the thickness of the gate dielectric used in conventional CMOS circuits. The current drive in a CMOS transistor is directly proportional to the gate capacitance. Since capacitance scales inversely with thickness, higher current drive requires continual reductions in thickness for conventional dielectrics. Present technology uses SiO
2
based films with thicknesses near 5 nm. However projections suggest the need for 2 nm films for future small geometry devices. SiO
2
gate dielectrics in this thickness regime pose considerable challenges from a manufacturing perspective. Process control of the growth of a 2 nm film requires unprecedented thickness control. At these thicknesses direct tunneling through the SiO
2
may occur, although the effect of tunneling current on device performance may not preclude operation. Since the tunnel current depends exponentially on the dielectric thickness, small variations in process control may result in large variations in the tunnel current, possibly leading to localized reliability problems. SiO
2
at these thicknesses also provides very little barrier to diffusion. Thus the diffusion of B from doped poly gates, for example, would represent an increasingly difficult problem that might also require a move to new gate dielectrics or gate metals.
The capacitance of a simple parallel plate dielectric with metal electrodes can be expressed as
C=&egr;&egr;
0
A/t
where &egr; is the dielectric permittivity, &egr;
0
so is the permittivity of free space, A is the capacitor area and t is the dielectric thickness. In general, the increase in capacitance density (C/A) required for increasing current drive can be accomplished either by decreasing the dielectric thickness t or by increasing the dielectric permittivity &egr; of the material. Thus, as with storage dielectrics, it is again desirable to change to a material with a higher permittivity.
SUMMARY OF THE INVENTION
Although dielectric permittivity is often referred to as the dielectric “constant” k, it is not a constant and may show strong variations with frequency, electric field or temperature. The magnitude of each of the dielectric mechanisms, as well as the speed with which they respond to changes in the applied field will vary. The space charge and dipole components show strong variations at frequencies of a few MHz and below. The ionic component is relatively constant for values well into the GHz region, while at optical frequencies the only remaining component is the electronic polarization. Consideration of these phenomena initially suggests that either ionic or electronic mechanisms may be preferred in high permittivity dielectrics for memory capacitors and gate dielectrics. Although most high permittivity dielectrics have dielectric constants greater than 50, some potentially useful dielectrics have lower permittivity. Thus, for the purposes of this application, high permittivity dielectrics will have dielectric constants greater than or equal to about 20.
This preference for dielectric mechanisms with high frequency response somewhat limits the field of practical high permittivity dielectric materials. This class of materials includes Ta
2
O
5
; Nb
2
O
3
; Y
2
O
3
; TiO
2
; (Ta
2
O
5
)
9
, (TiO
2
)
1
; ZrO
2
; HfO
2
; (Hf,Zr)O
2
; BaTiO
3
; SrTiO
3
; and (Ba,Sr)TiO
3
or BST. Even though some of these may be considered ferroelectric materials, each of these materials shows promise as a high-k dielectric.
This disclosure will focus on high-k dielectrics. However, many devices will provide suitable performance with elevated dielectric constant (k>7) materials such as Al
2
O
3
and Si
3
N
4
, and limited frequency response materials such as lead zirconate titanate (PZT). If performance requirements are satisfied, these dielectrics may be substituted for the high-k dielectrics in the examples below.
The semiconductor industry has tried for several years to integrate high permittivity (high-k) materials into integrated circuits. Although there has been much progress, these prior approaches each have drawbacks or limitations. One recurring problem is preventing unwanted layers from forming between the substrate or first electrode and the high-k dielectric. Unless these layers also have a high permittivity, the overall capacitance is reduced. This can be shown clearly with an illustrative example. For this example, we will use one promising high-k dielectric candidate, Ta
2
O
5
on a silicon layer. Other high-k materials will have different interface details, but will follow the same general analysis.
Ta
2
O
5
has a promising permittivity and reasonable bandgap. However, the lower heat of formation relative to SiO
2
immediately suggests that Ta
2
O
5
is not thermodynamically stable next to Si and will decompose to SiO
2
at the interface. The capacitance of 2 dielectrics in series (such as a Ta
2
O
5
dielectric layer on an interfacial SiO
2
layer) is given by
(1/
C
)=(1/
C
1
)+(1/
C
2
)
where C
1
and C
2
are the capacitances of the two layers. From equation 1 we can write (assuming equal area capacitors)
t/&egr;=t
1
/&egr;
1
+t
2
&egr;
2
where t
1
, t
2
represent the thicknesses of the two layers, &egr;
1
,&egr;
2
represent the permittivities of the two layers, and t and &egr; are the “effective” thickness and permittivity of the stack. A common parameter used to describe dielectric stacks is the equivalent oxide thickness of the capacitor. This is the theoretical thickness of SiO
2
that would be necessary to generate the same capacitance density as the material of interest (ignoring practical issues with thin SiO
2
films such as leakage or tunneling effects). Thus,
 
t
eq
(SiO2)=&egr;(SiO
2
)*[
t
1
/&egr;
1
+t
2
/&egr;
2
]
If the interfacial layer t
1
is SiO
2
, this equation can be rewritten as:
t
eq
(SiO
2
)=
t
1
+t
2
*[&egr;(SiO
2
)/&egr;
2
]
This equation shows that the equivalent (effective) oxide thickness of the stack (and hence the capacitance density) will be limited by the presence of a thin interfacial oxide. Thus, the effective oxide thickness will never be less than the thickness of the interfacial oxide. This minimum effective thickness is independent of the permittivity and thickness of the second layer. This finding is consistent with the extensive body of work performed to try to develop Ta
2
O
5
as a DRAM dielectric. According to Aoyama, in “Leakage current mechanism of amorphous and polycrystalline Ta
2
O
5
films grown by chemical vapor deposition.”
J. of Electrochemical Society,
1996. 143(3): p. 977-983, the minimum effective oxide thickness achievable with Ta
2
O
5
MIS capacitor structures using Si based electrodes is ~2.5 nm. This is due to the

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