Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-19
2002-01-01
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000, C438S733000
Reexamination Certificate
active
06335247
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to an integrated circuit (“IC”) and method of forming thereof, and more particularly to an integrated circuit vertical trench device and method of forming thereof.
BACKGROUND
The semiconductor industry is continuously trying to decrease the size of the semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today's semiconductor products. For example, it is not uncommon for there to be millions of semiconductor devices on a single semiconductor product.
Typically, the focus of miniaturization has been placed on the two-dimensional horizontal plane of a semiconductor device, and devices have approached sizes down to tenths of microns and less. There is some limit, however, as to how far a horizontally oriented semiconductor device can be shrunk, and as devices are made even smaller, it is generally becoming increasingly difficult to further miniaturize a device's horizontal dimensions. In addition, the decreasing horizontal dimensions of semiconductor devices generally tend to create problems in the operational characteristics of the semiconductor devices.
One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor memory is a dynamic random access memory (“DRAM”). A DRAM may include millions or billions of individual DRAM cells, each cell storing one bit of data. A DRAM memory cell typically includes an access field-effect transistor (“FET”) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
Semiconductor memory density is typically limited by a minimum lithographic feature size that is imposed by lithographic processes used during fabrication. There is a continuing need in the art to provide even higher density memories in order to further increase data storage capacity and reduce manufacturing costs.
One way of increasing the data storage capacity of semiconductor memories is to reduce the amount of integrated circuit horizontal planar area consumed by each memory cell. For horizontally oriented devices, this may be done by decreasing the size of the access FET or the storage capacitor, or both. This approach has limits, however, due to minimum producible structure size in a given fabrication technology, and the problems associated with devices with small dimensions, such as hot carriers, punch through, and excess leakage.
Another way of providing planar area reduction is the use of a three-dimensional arrangement of the access FET and the storage capacitor. One such arrangement is a planar FET next to a deep trench capacitor. A trench typically has a depth of 5-8 um and an oval top-down-view shape. The trench capacitor has plates which are located vertically along the walls of the trench instead of being parallel to the surface of the integrated circuit substrate. This permits a large capacitance per planar unit area of substrate, while at the same time allowing the device to be of a manageable size for purposes of operation.
To still further reduce the amount of planar area required for each cell, it has been proposed to use a vertical trench transistor in conjunction with a vertical trench capacitor in a memory cell. In a typical design, the vertical capacitor is generally fabricated in a trench, with one conductive plate being formed in the substrate, the dielectric being formed on the trench sidewalls, and the other conductive plate being formed in the interior of the trench. A vertical trench transistor is generally fabricated adjacent to an upper portion of the trench, with the source and drain being fabricated in the substrate, and the vertically-oriented gate being fabricated in the trench.
There are generally several problems, however, with prior art approaches to fabricating a vertical transistor in a DRAM cell. One difficult fabrication issue is related to formation of the vertically-oriented gate. Typically, the gate insulator is an oxide produced by thermal oxidation of the trench sidewall. The thickness of the gate insulator generally determines the threshold voltage required to turn on the device. Ideally, the gate insulator thickness should be uniform along the channel length and width.
The oxidation rate of the trench sidewall, however, is generally highly dependent upon the crystal plane orientation of the sidewall. In other words, different crystal planes may generate oxides of very different thicknesses when subjected to the same thermal oxidation process. In a trench formed in a substrate (e.g., a rounded (including oval) trench, top-down view), different crystal orientations are exposed to the oxidation process because the sidewalls cut through different crystal planes in the substrate. Thermal oxidation of the sidewalls thus results in different oxide thicknesses around the trench dependent upon crystal orientation. A non-uniform oxide thickness for the gate insulator may cause leakage. And other device reliability problems. In addition, the non-uniformity may cause inconsistent threshold voltages from device to device.
One proposal to alleviate this problem is to use a selective wet etch which etches, for example, the <100> crystal planes faster than the <110> crystal planes. This generally results in a rectangular trench shape with substantially only <110> planes, although small <100> planes may remain in the partially rounded corners. Thermal oxidation should then result in substantially uniform oxide thickness, except perhaps at the comers of the trench. While this process is more robust than previous processes, a potential problem with this approach is that the <110> planes are partially etched along with the <100> planes, albeit at a much slower rate. This may lead to a widening of the trench in the <110> plane direction, which may decrease the effective distance from the components (e.g., buried strap connection) of one trench to the components (e.g., isolation collar) of an adjacent trench.
SUMMARY OF THE INVENTION
These problems are generally solved or circumvented, and technical advantages are generally achieved, by a preferred embodiment of the invention in which a selective wet etch is used to etch only a part of the trench sidewalls. While a portion of the trench perimeter is protected by a mask, the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench. Then, a single side vertical device process may be used to form, for example, a single side vertical trench transistor on a flat sidewall having a single crystal plane. Because a portion of the trench is masked, the trench does not widen in that direction during the selective wet etch, and device to device isolation is improved over that achieved with previous methods.
In accordance with a preferred embodiment of the present invention, a DRAM IC comprises a deep trench located in a semiconductor substrate, the trench having an upper portion with a perimeter comprising a rounded side and a flat side opposite the rounded side. The flat side of the perimeter of the trench comprises a flat substrate sidewall with a substantially single crystal plane, and a vertically-oriented device is located on the flat substrate sidewall. The vertically oriented device is preferably a transistor with a vertical gate oxide formed on the flat substrate sidewall.
In accordance with another preferred embodiment of the present invention, a method of forming a vertically oriented device in a deep trench on a semiconductor substrate, the trench comprising a rounded perimeter, comprises masking a first region of a substrate sidewall in the trench, wherein a second region of the substrate sidewall in the trench is exposed, the second region comprising multiple sub
Kudelka Stephan
Lee Brian S.
Michaelis Alexander
Schroeder Uwe
Tews Helmut Horst
Elms Richard
Infineon - Technologies AG
Smith Bradley
Stanton Braden
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