Integrated circuit test systems that use direct current...

Details Integrated circuit test systems that use direct current... Integrated circuit test systems that use direct current...

1999-09-01

2002-11-19

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S063000, C365S189090

Reexamination Certificate

active

06483758

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 98-36934, filed Sep. 8, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuit testing, and, more particularly, to systems for testing integrated circuit memory modules and devices.
BACKGROUND OF THE INVENTION
Improvements in both speed and functionality of central processing units (CPUs) have generally resulted in accompanying improvements in memory devices to support the operation of these improved CPUs. These memory devices may comprise a plurality of integrated circuit memory elements. That is, a single memory module may include a plurality of conventional or “normal” memory elements. Unfortunately, the fabrication process may damage one or more of the conventional memory elements that comprise the memory module. Therefore, it may be desirable to test the various memory elements within a memory module to identify any elements that are inoperable.
FIG. 1
is a high-level block diagram that depicts a conventional testing system for verifying the operation of a memory module. A test unit
100
includes both the hardware and software for controlling the testing operation. The test unit
100
interfaces with a load board
120
that is used for transmitting signals output from the test unit
100
. A socket printed circuit board
140
and socket
160
are used to interface the load board
120
to a memory module
180
.
Broadly stated, the test unit
100
is used to test the memory module
180
as follows: The test unit
100
provides a read instruction and/or a write instruction to one or more memory elements within the memory module
180
through the load board
120
, printed circuit board
140
, and socket
160
. The test unit
100
can then determine whether a particular memory element within the memory module
180
is operating properly by comparing data written into a memory cell with data read from the memory cell to determine if they are identical.
FIG. 2
is a schematic of a conventional test configuration using independent channel signaling that illustrates the test unit
100
, load board
120
, and memory module
180
in more detail. The test unit
100
includes a plurality of data input drivers
12
-
1
,
12
-
3
, . . . , and
12
-(
2
n-
1
) that receive control signals and address data through the input terminals
10
-
1
,
10
-
5
, . . . , and
10
-(
4
n-
3
). The test unit
100
further includes a plurality of data input drivers
12
-
2
,
12
-
4
, . . . , and
12
-
2
n that receive write data through the input terminals
10
-
2
,
10
-
6
, . . . , and
10
-(
4
n-
2
). Finally, the test unit
100
includes a plurality of comparators
14
-
1
,
14
-
2
, . . . , and
14
-n that are used to compare read data from the memory module
180
with expected data provided through the input terminals
10
-
4
,
10
-
8
, . . . , and
10
-
4
n and to generate a comparison result at the output terminals
10
-
3
,
10
-
7
, and
10
-(
4
n-
1
).
The load board
120
includes a plurality of transmission lines
20
-
1
,
20
-
3
, . . . , and
20
-(
2
n-
1
) that are connected to the output terminals of the data input drivers
12
-
1
,
12
-
3
, . . . , and
12
-(
2
n-
1
). In addition, the load board
120
includes a plurality of transmission lines
20
-
2
,
20
-
4
, . . . , and
20
-
2
n that are connected to the output terminals of the data input drivers
12
-
2
,
12
-
4
, . . . , and
12
-
2
n and one of the input terminals of the comparators
14
-
1
,
14
-
2
, . . . , and
14
-n as illustrated.
The memory module
180
includes a plurality of memory devices or elements
32
-
1
,
32
-
2
, . . . , and
32
-n that include input pins
30
-
1
,
30
-
3
, . . . , and
30
-(
2
n-
1
) and input/output pins
30
-
2
,
30
-
4
, . . . , and
30
-
2
n. The input pins
30
-
1
,
30
-
3
, . . . , and
30
-(
2
n-
1
) are connected to the transmission lines
20
-
1
,
20
-
3
, . . . , and
20
-(
2
n-
1
) and the input/output pins
30
-
2
,
30
-
4
, . . . , and
30
-
2
n are connected to the transmission lines
202
,
20
-
4
, . . . , and
20
-
2
n. For purposes of illustration, the memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n are each depicted with a single input pin and a single input/output pin. It is nevertheless understood to those skilled in the art that the memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n typically include both a plurality of input pins and input/output pins.
A method that may be used for testing the memory module
180
is described hereafter. A typical test cycle involves the following steps: 1) input the write instruction and the write address, 2) perform a data write operation, 3) input the read instruction and read address, and 4) perform a data read operation. This cycle may be repeatedly performed until the operability of all memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n in the memory module
180
is verified. This test cycle will be discussed hereafter with reference to the independent channel test configuration of FIG.
2
.
The test unit
100
receives the write instruction and write address through the input terminals
10
-
1
,
10
-
5
, . . . , and
10
-(
4
n-
3
). The write instruction and write address are then provided to the input pins
30
-
1
,
30
-
3
, . . . , and
30
-(
2
n-
1
) of the memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n through the data input drivers
12
-
1
,
12
-
3
, . . . , and
12
(
2
n-
1
) and the transmission lines
20
-
1
,
20
-
3
, . . . , and
20
-(
2
n-
1
). Next, the memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n prepare for the write operation.
The data to be written into the selected memory cell is received through the input terminals
10
-
2
,
10
-
6
, . . . , and
10
-(
4
n-
2
) and is provided to the input/output pins
30
-
2
,
30
-
4
, . . . , and
30
-
2
n of the memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n through the data input drivers
12
-
2
,
12
-
4
, . . . , and
12
-
2
n and the transmission lines
20
-
2
,
20
-
4
, . . . , and
20
-
2
n. The memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n then enable the data to be written into the selected memory cell.
After completing the data write operation, the test unit
100
receives the read instruction and read address through the input terminals
10
-
1
,
10
-
5
, . . . , and
10
-(
4
n-
3
) and, simultaneously, the data that has been previously written into the memory cell corresponding to the read address is received at the input terminals
10
-
4
,
10
-
8
, . . . , and
10
-
4
n. The read instruction and read address are provided to the input pins
30
-
1
,
30
-
3
, . . . , and
30
-(
2
n-
1
) of the memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n through the data input drivers
12
-
1
,
12
-
3
, . . . , and
12
-(
2
n-
1
) and the transmission lines
20
-
1
,
20
-
3
, . . . , and
20
-(
2
n-
1
). Next, the memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n prepare for the read operation.
The data are then read through the input/output pins
30
-
2
,
30
-
4
, . . . , and
30
-
2
n and transmission lines
20
-
2
,
20
-
4
, . . . , and
20
-
2
n traversing the same path that was used to write data to the memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n. The data that are read from the memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n are compared by the comparators
14
-
1
,
14
-
2
, . . . , and
14
-n with the expected data provided at the input terminals
10
-
4
,
10
-
8
, . . . , and
10
-
4
n. The results of the comparison are provided through the output terminals
10
-
3
,
10
-
7
, and
10
-(
4
n-
1
).
The test unit
100
uses the results of the comparison operation to determine whether the memory devices
32
-
1
,
32
-
2
, . . . , and
32
-n are operating properly. More specifically, if a comparison result indicates that the read data and the expected data are identical, then the test unit
100
concludes that a particular memory device
32
-
1
,
32
-
2
, .

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