Integrated circuit structure having contact openings and vias fi

Details Integrated circuit structure having contact openings and vias fi Integrated circuit structure having contact openings and vias fi

1996-06-17

1998-12-08

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257771, 257774, 257764, 257760, H01L 2348, H01L 2352, H01L 2940

Patent

active

058474617

ABSTRACT:
A process and resulting structure are described for using a metal layer formed over an insulating layer as both the filler material to fill openings in the insulating layer and as the patterned metal interconnect or wiring harness on the surface of the insulating layer. The process includes the steps of forming a compressively stressed metal layer over an insulating layer having previously formed openings therethrough to the material under the insulating layer; forming a high tensile strength cap layer of material over the compressively stressed metal layer; and then heating the structure to a temperature sufficient to cause the compressively stressed metal layer to extrude down into the openings in the underlying insulating layer. The overlying cap layer has sufficient tensile strength to prevent or inhibit the compressive stressed metal layer from extruding upwardly to form hillocks which would need to be removed, i.e., by planarization. The temperature to which the compressively stressed metal layer is subsequently heated to cause it to extrude should be less than the melting point of the compressively stressed metal layer.

REFERENCES:
patent: 4587138 (1986-05-01), Yau et al.
patent: 5288664 (1994-02-01), Mukai
patent: 5409862 (1995-04-01), Wada et al.
patent: 5427982 (1995-06-01), Jun
patent: 5563448 (1996-10-01), Lee et al.

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