Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
1999-11-09
2001-07-31
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S701000, C257S702000, C257S710000
Reexamination Certificate
active
06268654
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit packages, and in particular to a low cost, integrated circuit package.
BACKGROUND OF THE INVENTION
A goal in packaging integrated circuits is to reduce the cost and difficulty of manufacturing reliable packages. This goal is particularly present in packaging erasable programmable read-only memory devices (“EPROM”), charge coupled devices (“CCD”), and the like. Each such device requires a transparent package surface above the die, such as a quartz window, which increases manufacturing cost and difficulty.
A conventional package for an EPROM device, for example, has a ceramic base and an opposing ceramic lid. The base and/or lid have central depressions. When the base and lid are opposed, the depression(s) define a cavity for the die. The ceramic portions of the base and lid form the sides of the package. The lid has an aperture into which a glass or quartz window is fitted. A conductive metal lead frame is sandwiched between the base and lid. The leads of the lead frame perforate the sides of the package, extending laterally into and away from the cavity. Inside the cavity, the leads are connected to the die by bond wires. Thin layers of frit seal glass bond the base and lid to the lead frame and thus to each other.
Such packages have cost disadvantages, such as the need for a two-piece lid and a lead frame permeating the sides of the package. These and other cost and manufacturability disadvantages are also present in other EPROM packages, such as those shown in U.S. Pat. Nos. 5,043,004 and 5,192,681.
SUMMARY OF THE INVENTION
The present invention includes a package enclosing one or more integrated circuit die, and a method for making such a package. The package is useful, for example, in SAW, EPROM and CCD applications.
A package in accordance with one embodiment of the invention has an insulating substrate as a base upon which a die is placed; an imperforate adhesive bead surrounding the die as the package sidewalls; and a lid, centered over and spaced above the substrate and die, in press-fitted interconnection with the bead.
The substrate has a substantially planar first surface upon which at least one integrated circuit die is placed, and an opposing second surface. Conductive structures on the substrate, and conductive vias through the substrate, provide electrical connectivity between the die and external circuitry.
The imperforate adhesive bead is applied onto the first surface of the substrate. The bead surrounds the integrated circuit die. The bead is initially viscous, but is hardenable into a solid. Epoxy material or an equivalent such as silicone or a blend of such materials is used for the bead.
The lid is plastic or ceramic for surface acoustical wave (“SAW”) package applications. Alternatively, for EPROM or CCD applications, the lid is transparent, at least in part, to a selected electromagnetic radiation, such as ultraviolet, visible, or infrared light. Boro-silicate glass is suitable. The lid has a first surface that faces and is spaced above the first surface of the substrate and the integrated circuit die. A peripheral portion of the first surface of the lid is in a press-fitted interconnection with the bead.
The lid has an edge at its perimeter which is also in press-fitted interconnection with the bead. The lid's edge has perpendicular, or alternatively, a sloped orientation, relative to the first and/or second surfaces of the lid. All or part of the edge portions are in press-fitted interconnection with the bead.
One embodiment of a method of making such a package involves a first step of providing a substrate, such as described above, having a substantially planar first surface and at least one conductive structure on that first surface, and placing at least one integrated circuit die on the first surface of the substrate. The integrated circuit die is electrically connected to one or more of the conductive structures on the first surface of the substrate. A viscous, hardenable, adhesive material, such as epoxy, is applied on the first surface of the substrate to form an imperforate bead around the integrated circuit die(s). The bead extends to a height above the first surface of the substrate which is greater than the height of the integrated circuit die above the substrate.
A lid is also provided. For EPROM or CCD applications, at least part of the lid is transparent to electromagnetic radiation, for example, infra red, ultraviolet, or visible light. For example, a flat, one piece boro-silicate glass lid is used.
The lid is placed onto the bead while the bead is still viscous, so that the first surface of the lid is facing, centered over, and spaced above the first surface of the substrate and the integrated circuit die. A peripheral portion of the first surface of the lid makes contact with the top surface of the bead. The lid is then press-fit into the bead, such as by mechanical pressing. All or part of the edge of the lid is also press fit into the bead, so that the bead material contacts all or part of the edge of the lid. The bead is then hardened, such as by heating the package.
In an alternative method embodiment, a viscous material is applied to the first surface of the substrate to form an imperforate bead substantially around the integrated circuit, leaving at least one discontinuity, e.g., a gap. Additional viscous adhesive material is then applied to the package, after the lid is placed onto and press-fitted into the bead and after the bead partially hardens, to fill any gaps in the bead. The adhesive bead is an epoxy material or equivalent, and the lid is a flat, one-piece boro-silicate glass plate.
An alternative embodiment of the package includes an integrated circuit which is attached to a metal die pad on the planar first surface of a substrate. The metal die pad extends laterally beyond the entire perimeter of the integrated circuit die. The package also has a conductive path which passes through the substrate for conducting an electrical signal(s) between a conductive structure on the integrated circuit die, such as a bonding pad(s), and a conductive structure on the second surface of the substrate, such as an interconnection ball(s). The bonding pads are covered with a nonconductive adhesive material to prevent corrosion. A nonconductive adhesive bead on the first surface of the substrate surrounds the integrated circuit die and covers a peripheral portion of the metal die pad around the entire perimeter of the metal die pad. A lid having a planar first surface is placed on and connected to the adhesive bead around the integrated circuit die and is supported above the first surface of the substrate and the integrated circuit die by the bead. optionally, the package has vertical peripheral sides around the entire package
The placement of the bead relative to the integrated circuit die may vary. In one embodiment, the adhesive bead contacts all sides of the die and covers a peripheral portion of the first surface of the integrated circuit die around the entire perimeter of the integrated circuit die. In this embodiment, the adhesive bead, rather than a separate adhesive coating, covers the conductive structures, such as bonding pads, on the first surface of the integrated circuit die. The adhesive bead also may cover bond wires or other types of conductive structures which are attached to bonding pads.
A method of making a plurality of integrated circuit die simultaneously is also described. A first step includes providing a generally planar first sheet of an insulating material suitable for forming package substrates. The first sheet of substrate material has a plurality of physically-joined package substrates in a matrix. Each package substrate has a planar first surface in a common plane. A second step is placing an integrated circuit die on a metal die pad formed on the first surface of each package substrate of the first sheet. A third step is electrically connecting a conductive structure, such as a bonding pad, on each of the die to a conductive
Glenn Thomas P.
Hollaway Roy D.
Panczak Anthony E.
Ankor Technology, Inc.
Booth Richard
Parsons James E.
Skjerven Morrill & MacPherson LLP
Zarneke David A
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