Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1997-12-17
2001-01-23
Thai, Luan (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S685000, C257S780000, C257S723000, C257S724000
Reexamination Certificate
active
06177723
ABSTRACT:
This application claims priority under 35 USC § 119 of the Singapore application number 970115-9 filed Apr. 10, 1997.
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of integrated circuit packages and more particularly to a substantially flat integrated circuit package employing an improved molding process for encapsulating a chip in a cavity on a substrate board.
BACKGROUND OF THE INVENTION
In the manufacture and assembly of integrated circuits, first, the integrated circuits are formed on semi-conductor wafers. The wafers are separated into individual chips and the individual chips are then handled and packaged. The packaging process is one of the most critical steps in the integrated circuit fabrication process, both from the point of view of cost and of reliability, in that the packaging cost can easily exceed the cost of the integrated circuit chip, and the majority of device failures are packaging oriented.
A key step in the integrated circuit fabrication is packaging the chip in a suitable medium that will protect it in subsequent manufacturing steps and from the environment of its intended application. In the typical packaging process, there are two main steps: wire bonding and encapsulation. Wire bonding connects the leads from the chip to the terminals of the package. The terminals allow the integrated circuit package to be connected to other components of the device. Following wire bonding, encapsulation is employed to seal the surfaces from moisture and contaminants and to protect the wire bonds and other components from corrosion and mechanical shock.
The packaging of integrated circuits has generally involved attaching an individual chip to a lead frame, where, following wire bonding and encapsulation, designated parts of the lead frame become the terminals of the package. The packaging of integrated circuits has also involved the placement of a chip on a flexible board where, following adhesion of the chip to the surface of the flexible board and wire bonding, an encapsulant is placed over the chip and the adjacent flexible board to seal and protect the chip and other components.
Known integrated circuit packaging techniques include the dual in-line package (DIP), the pin grid array (PGA), and the leadless chip carrier (LCC). With these known packaging techniques, the chips employ bonding pads on the outer circumference of the chip. This results in long leads from the bonding pads to the chip's circuitry.
The known integrated circuit packaging techniques have several disadvantages, particularly with regard to the encapsulation step. In the known techniques, the chip is placed on a lead frame or a flat surface of a flexible board, then a molding process is employed to place an encapsulant over the silicon chip. The molding process generally involves two plates which press against the lead frame or board and attached chip and, with reference to that plate placed adjacent to the chip, the plate includes a mold cavity for molding encapsulant over and around the chip. In addition to the mold cavities, these plates also have intricate conduits for providing the encapsulant to the mold cavity, commonly called main runners, subrunners and gates. The main runner provides encapsulant to a multitude of mold cavities; the subrunners provide encapsulant to individual mold cavities; and the gates provide a reduced cross-sectional area where, following the completion of the molding process, the cured encapsulant is cut.
The known techniques for molding encapsulant over a chip attached to a lead frame or the surface of a flexible board have several significant shortcomings. First, when converting from one package design to a second, different package design, the mold plates with integral mold cavities, gates, subrunners and main runner would often be required to be redesigned from the first package design to the second package design, as generally, the mold cavities in the plate would not align with the second design's placement of the chip on the lead frame or flexible board. Thus, there was significant design, engineering, expense, and lag time in redesigning molding plates when changing from a first packaging design to a second packaging design. Additionally, the encapsulation of a chip on a lead frame or on the surface of a flexible board requires an undue amount of encapsulant. Further, the protrusion of the chip beyond the board detracts from the package's protection in subsequent manufacturing and testing steps and from the environment of its intended application.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for an integrated circuit package and a molding process for encapsulating integrated circuit packages which avoids the placement of the chip on the exterior surface of a flexible board.
In accordance with the present invention, a molding process is provided that significantly improves the ability for a manufacturer to move from a first integrated circuit packaging design to a second integrated circuit packaging design. The present invention provides a flexible board having a cavity for silicon chip attachment, with the molding plates being flat or “cavityless”. Thus, when moving from a first packaging design to a second packaging design, the molding plates need not be replaced or redesigned. This provides significant flexibility, cost, and lag time advantages when changing packaging designs. Additionally, the molding process reduces the encapsulant usage and provides additional protection to the chip and its electrical connections to the flexible board.
The present invention provides that the chip's bonding pads are located in a central area on the chip. This provides a significant advantage in allowing for short leads between the bonding pads and the chip's memory circuits. This can advantageously be used to increase a chip's memory capacity.
The integrated circuit package includes a base with a top opening and a cavity. Routing strips electrically connect the top opening to exterior connections. A chip with bonding pads located in a central area of the chip is adhered in the cavity and wire bonding is used to electrically connect the routing strips in the top opening with the bonding pads. The top opening and cavity are then filled with encapsulant to form a substantially flat integrated circuit package.
The molding process includes placing the pre-encapsulated assembly in a mold having flat upper and lower molding plates. The lower molding plate has a mold gate, and encapsulant is added through the mold gate to substantially fill the top opening and the cavity.
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Chan Boon Pew
Chan Min Yu
Eng Kian Teng
Goh Jing Sua
Honeycutt Gary C.
Telecky Fred
Texas Instruments Incorporated
Thai Luan
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