Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
2000-02-22
2002-04-02
Reichard, Dean A. (Department: 2831)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C174S050510, C257S691000, C257S738000, C257S778000, C257S686000
Reexamination Certificate
active
06365833
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to the field of high frequency integrated circuit packages and more specifically to an apparatus and method of using an adhesive material to attach a silicon chip to a substrate and to provide a protective coverage around the chip.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described in connection with integrated circuit packages, as an example.
Heretofore, in this field, integrated circuits have been formed on semiconductor wafers. The wafers are separated into individual chips and the individual chips are then handled and packaged. The packaging process is one of the most critical steps in the integrated circuit fabrication process, both from the point of view of cost and of reliability. Specifically, the packaging cost can easily exceed the cost of the integrated circuit chip and the majority of device failures are packaging related.
The integrated circuit must be packaged in a suitable medium that will protect it in subsequent manufacturing steps and from the environment of its intended application. Wire bonding and encapsulation are the two main steps in the packaging process. Wire bonding connects the leads from the chip to the terminals of the package. The terminals allow the integrated circuit package to be connected to other components. Following wire bonding, encapsulation is employed to seal the surfaces from moisture and contamination and to protect the wire bonding and other components from corrosion and mechanical shock.
Conventionally, the packaging of integrated circuits has involved attaching an individual chip to a lead frame, where, following wire bonding and encapsulation, designated parts of the lead frame become the terminals of the package. The packaging of integrated circuits has also involved the placement of chips on a flexible board where, following adhesion of the chip to the surface of the flexible board and wire bonding, an encapsulant is placed over the chip and the adjacent flexible board to seal and protect the chip and other components.
Unfortunately, current methods for encapsulating silicon chips have led to various problems, including cracking between the encapsulation material and the integrated circuit components, as well as high failure rates due to the multi-step nature of the process. Cracking has plagued the industry because of differences in the coefficient of thermal expansion of the different components, for example, between the soldering materials at the different interfaces and between metallic and non-metallic components. Cracking is also frequent between the silicon wafer and the encapsulation materials, usually epoxies, due to the extreme variations in temperature in various environments and between periods of operation and non-operation.
Even if the encapsulated silicon chip is successfully assembled into a working integrated circuit, another problem is commonly encountered. Once the silicon chip is encapsulated it is typically surface mounted using radiant heat or vapor saturated heating. This process, however, can lead to poor coplanarity due to uneven reflow, leading to integrated circuit failure.
Therefore, a need has arisen for an integrated circuit package and a process for producing an integrated circuit package wherein a single material may be used to adhere the chip to the flexible board and protect the chip during subsequent manufacturing and testing steps as well as from the environment of its intended purpose. A need has also arisen for a smaller, more versatile integrated circuit package made from materials and by methods that lead to increased yield by more closely matching the coefficient of thermal expansion of the materials used in the package.
SUMMARY OF THE INVENTION
The present invention disclosed herein comprises an integrated circuit package and a process for producing an integrated circuit package that protects the silicon chip during manufacturing and testing steps and from the environment of its intended purpose using the same material that adheres the silicon chip to the printed circuit board.
The integrated circuit package is produced by placing an adhesive material on one surface of a substrate then placing a chip in contact with the adhesive material such that the chip is adhered to the substrate by the adhesive material and such that a seal is provided around the perimeter of said chip by the adhesive material to protect said chip.
The substrate has an opening and first and second surfaces. A plurality of routing strips are integral with the substrate and extend into the opening. A plurality of pads are disposed on the first surface, at least one of the pads is electrically connected with at least one of the routing strips. The chip has at least one bonding pad. Wire bonding electrically connects the bonding pad to at least one of the routing strips. Potting material fills the opening. At least one solder ball is attached to at least one of the pads disposed on the first surface.
The process of attaching the chip to the substrate also includes positioning the chip in contact with the adhesive layer, placing the chip on a mounting stage, applying heat to the chip, applying a force to the chip, and flowing the adhesive around the perimeter of the chip. In one embodiment of the present invention the temperature applied to the chip is between about 200° C. and 250° C. and may preferably be about 220° C. In one embodiment of the present invention the force applied to the chip may be between about 150 and 200 grams and preferably about 175 grams. The force may be applied for between about 2 and 10 seconds and preferably for about 5 seconds.
REFERENCES:
patent: 5701233 (1997-12-01), Carson et al.
patent: 5739585 (1998-04-01), Akram et al.
Chan Boon Pew
Chan Min Yu
Eng Kian Teng
Goh Jing Sua
Low Siu Waf
Brady III Wade James
Ngo Hung V
Reichard Dean A.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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