Integrated circuit memory devices having synchronized bit line s

Details Integrated circuit memory devices having synchronized bit line s Integrated circuit memory devices having synchronized bit line s

1998-11-17

2000-02-08

Phan, Trong

Static information storage and retrieval

Read/write circuit

Precharge

365207, 365233, G11C 700, G11C 702, G11C 800

Patent

active

060234369

ABSTRACT:
Integrated circuit memory devices having synchronized bit line selection and I/O line precharge capability include an array of memory cells, a pair of differential bit lines electrically coupled to the array of memory cells, a pair of differential input/output lines and a sense amplifier electrically coupled to the pair of differential input/output lines. An equalization circuit is also provided to equalize the potentials of the pair of differential input/output lines in response to a precharge enable signal. A column select circuit is provided to electrically connect the pair of differential bit lines to the pair of differential input/output lines, in response to a column select enable signal. In addition, a control signal generator is provided to generate the column select enable signal and the precharge enable signal during nonoverlapping time intervals and in-sync with an external clock signal. Using these circuits, the timing margins (e.g., overplus operation margin) associated with the enabling of the precharge signal upon the disabling of the column select signal can be advantageously reduced to enable higher speed operation.

REFERENCES:
patent: 5233560 (1993-08-01), Foss et al.
patent: 5247482 (1993-09-01), Kim
patent: 5561630 (1996-10-01), Katoh et al.
patent: 5870343 (1999-02-01), Chi et al.

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