Integrated circuit memory devices and testing methods including

Details Integrated circuit memory devices and testing methods including Integrated circuit memory devices and testing methods including

1998-11-24

2000-03-14

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Testing

36518902, 36518907, G11C 700

Patent

active

060381825

ABSTRACT:
Integrated circuit memory devices and testing methods include a plurality of control signals, a respective one of which corresponds to a respective one of a plurality of input/output channels, and activates a selected one of the plurality of input/output channels in response to activation of a selected one of the plurality of control signal inputs during a test mode. All of the plurality of input/output channels may be activated in response to activation of all of the plurality of control signals inputs during a normal mode. Accordingly, a selected one of the data input/output channels may be activated for reduced data path width testing. By sequentially activating a selected one of the data input/output channels, all the circuits of the memory device related to the data input/output channels may be tested.

REFERENCES:
patent: 5717643 (1998-02-01), Iwanami et al.
patent: 5748641 (1998-05-01), Ohsawa
patent: 5793686 (1998-08-01), Furutani et al.
patent: 5793687 (1998-08-01), Deans et al.

Affiliated with

Also associated with

Rating

Integrated circuit memory devices and testing methods including does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit memory devices and testing methods including , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit memory devices and testing methods including will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-175808