Integrated circuit device including a scan test circuit and...

Details Integrated circuit device including a scan test circuit and... Integrated circuit device including a scan test circuit and...

2007-07-24

2007-07-24

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10696090

ABSTRACT:
Integrated circuit devices include a core block having a plurality of output ports and a plurality of input ports and a vector input terminal. The core block generates core internal data responsive to output data from the input ports and is configured to output the core internal data during scan testing and to selectively generate core output data for the output ports responsive to the core internal data or to test vector serial input data from the vector input terminal. An input side sub logic circuit unit generates sub data for the plurality of input ports responsive to data input to the first sub logic circuit unit. A multiplexer (MUX) unit between the core block and the first sub logic circuit unit selectively provides the sub data or the output data as inputs to the input ports of the core block responsive to a MUX control signal.

REFERENCES:
patent: 5774476 (1998-06-01), Pressly et al.
patent: 6816990 (2004-11-01), Song et al.
patent: 6877122 (2005-04-01), Whetsel
patent: 6988228 (2006-01-01), Paglieri

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