Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-01
2001-09-04
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S253000, C438S396000
Reexamination Certificate
active
06284586
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit device, preferably a capacitor, and a method of making the same, and, more particularly, an integrated circuit capacitor for mixed signal applications that is made using chemical mechanical polishing.
2. Background Information
Capacitors are necessary for many analog and digital integrated circuit applications. Further, certain applications require series parallel combinations of integrated circuit capacitors. One such application is mixed signal applications, in which switched and capacitor filter, analog-to-digital or digital-to- analog converters, charge distribution networks or analog or sampled data functions are performed on an integrated circuit chip.
While there are many known techniques for forming integrated circuit capacitors, such techniques are characterized by the use of plural numbers of mask steps. Such mask steps inherently create undesired alignment variables such that the fabrication of integrated circuit chips containing integrated circuit capacitors is very difficult as well as increase product cost. Further, fabrication of integrated circuit capacitors using known methods also tends to result in other undesired characteristics, such as surface topologies having peaks and valleys which make the proper formation of subsequent layers difficult. For example, the formation of a subsequent metal patterning layer over a surface having peaks and valleys tends to cause inconsistencies in the individual conductive paths that are part of the metal patterning layer. Further, formation of conventional capacitors tends to adversely impact on thermal considerations, especially for devices operating in the deep sub micron region. While methods are known to overcome certain of these undesired characteristics, such as the topology problem noted above, such conventional methods tend to be overly complicated and, as a result, difficult to practically implement and/or undesireably expensive to implement.
Further, other circuit devices having formation characteristics similar to that of integrated circuit capacitors also suffer from many of the same fabrication problems.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a simple method of forming an integrated circuit device, preferably a capacitor.
Another object of the present invention is to provide a method of forming an integrated circuit device that adds only a single additional masking step to the fabrication process and reduces problems relating to alignment of various layers.
It is another object of the present invention to use chemical-mechanical polishing to assist in the formation of a self-aligned integrated circuit device.
It is still a further object of the present invention to obtain an integrated circuit capacitor, as well as other integrated circuit devices, which can be embedded at various layers of the integrated semiconductor chip.
It is still another object of the present invention to obtain integrated circuit capacitors that can be isolated from and stacked on top of each other on the same integrated semiconductor chip, and made by simply repeating the method used to form the device.
In order to attain the above recited objects of the present invention, among others, the method of forming an integrated circuit capacitor according to the present invention forms a relatively thick insulation layer over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region of the dielectric layer and between a peripheral region which remains of the dielectric layer.
With this method, an integrated circuit capacitor results that can be embedded at various levels, as desired by the designer. Further, by repeating the application of dielectric, conductive and semiconductive layers prior to the step of chemical mechanical polishing, various other integrated circuit device structures, such as floating gate devices or diodes, can also be fabricated.
Furthermore, an integrated circuit capacitor or other integrated circuit device can be embedded at different desired locations in the integrated semiconductor chip, as well as be stacked on top of each other, by simply repeating the fabrication method at a different layer. Thus, the capacitor can be connected to various types of integrated circuit devices, for example resistors, diodes, and transistors, such as MOS or TFT types.
REFERENCES:
patent: 5949100 (1999-07-01), Oh et al.
patent: 6074907 (2000-06-01), Oh et al.
patent: 6075266 (2000-06-01), Yoshitomi
patent: 6081417 (2000-06-01), Matsuki
patent: 6083805 (2000-06-01), Ouellet et al.
Allman Derryl D. J.
Gregory John W.
Kwong Dim Lee
Seliskar John J.
Yakura James P.
Chaudhuri Olik
LSI Logic Corporation
Pham Hoai
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