Method forming shallow trench isolation

Details Method forming shallow trench isolation Method forming shallow trench isolation

1999-01-22

2001-07-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S426000, C438S437000

Reexamination Certificate

active

06258692

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority benefit of Taiwan application serial no. 87118024, filed Oct. 30, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor manufacturing method, and in particular to a method of forming shallow trench isolation (STI).
2. Description of the Related Art
Device isolation regions are used to prevent carriers from flowing between any two adjacent devices. Typically, the device isolation regions are formed between field effect transistors (FETs) in integrated circuit (IC) to reduce current leakage created therebetween. Traditionally, the device isolation regions are formed by LOCOS. Since LOCOS technique has increasingly matured, device isolation regions with a high reliability and efficiency can be formed with a low cost. However, the device isolation regions formed by LOCOS have the disadvantages of stress, a bird's beak surrounding each isolation region and thickness variation in different width areas. In particular, the bird's beak prevents the close packing of each device in high-density ICs. Therefore, in high-density ICs, it is necessary to use a shallow trench isolation structure that can be easily reduced in size instead of the traditional isolation structure.
In a method of forming shallow trench isolation, trenches are first formed in a substrate by anisotropic etching and then completely filled by oxide. Since the size of the formed shallow trench isolation regions can be reduced, bird's bread encroachment caused by LOCOS can be prevented. Therefore, it is an ideal isolation method suitable for manufacturing CMOS in sub-micron processes.
FIGS. 1A
to
1
E are schematic, cross-sectional views showing a method of forming shallow trench isolation according to the prior art.
Referring to
FIG. 1A
, a pad oxide layer
102
is first formed on a substrate
100
by thermal oxidation, wherein the pad oxide layer
102
is used to protect the surface of the substrate
100
. A silicon nitride layer
104
is formed on the pad oxide layer
102
by low pressure chemical vapor deposition (LPCVD).
Referring to
FIG. 1B
, a photoresist layer (not shown) is formed on the silicon nitride layer
104
by photolithography and etching. The silicon nitride layer
104
, the pad oxide layer
102
and the substrate
100
are etched in sequence to form a patterned silicon nitride
104
a
and a patterned pad oxide layer
102
a
with trenches
106
,
108
formed in the substrate
100
. Afterwards, the photoresist layer is removed.
Referring to
FIG. 1C
, a liner layer
110
is formed on the surfaces of the trenches
106
,
108
by high-temperature thermal oxidation, wherein the liner layer
110
extends to the top corners
120
of the trenches
106
,
108
to contact the patterned pad oxide layer
102
a.
An insulating layer
116
, such as s silicone oxide layer, is formed over the substrate
100
, and completely fills the trenches
106
,
108
by atmospheric pressure chemical vapor deposition (APCVD). Next, densification is performed on the insulating layer
116
in a nitrogen environment at a high temperature.
Referring to
FIG. 1D
, part of the insulation layer
116
is removed by chemical mechanical polishing using the patterned silicon nitride layer
104
a
as a polishing stop layer.
Referring to
FIG. 1E
, the patterned silicon nitride layer
104
a
is removed by wet etching with a hot phosphoric acid solution to expose the patterned pad oxide layer
102
a.
Then, the patterned pad oxide layer
102
a
is removed by wet etching using a hydrofluoric acid (HF) solution, thereby forming isolation regions
118
a,
118
b.
However, the trenches
106
,
108
having various densities and areas can affect the uniformity of chemical mechanical polishing. Furthermore, over-polishing is required to ensure that no insulating residue remains on the patterned silicon nitride layer
104
a,
causing a dish
130
to form in an isolation region
116
b,
called a dishing effect, as shown in FIG.
1
D.
Additionally, to prevent the sidewalls of the trenches
106
,
108
from oxidizing during densification, which oxidation causes stresses to accumulate, leading to the generation of manufactured devices leakage currents, densification is performed on the insulating layer
116
in a high-temperature nitrogen environment instead of in a high-temperature oxygen environment in which a denser insulating layer can be obtained. However, since the insulating layer
116
densified in a nitrogen environment has a looser structure and an etching rate higher than the patterned pad oxide layer
102
a,
and a factor of isotropic etching exists, pits
140
which can result in the kink effect are formed on the top corners
120
during wet etching using a hydrofluoric acid solution for removing the patterned pad oxide layer
102
a,
called a kink effect. The kink effect not only reduces threshold voltage, but also creates manufactured devices current leakage together with the formation of corner parasitic MOSFETs.
Additionally, during chemical mechanical polishing for planarizing the insulating layer
116
as shown in
FIGS. 1D and 1E
, particles in the polishing agent causes microscratches
150
on the surfaces of insulating layers
116
a
and
116
b.
The microscratches
150
becomes deeper and wider during wet etching using a hydrofluoric acid solution for removing the patterned pad oxide layer
102
a,
causing a bridging effect between the poly gates of two active regions on both sides of the isolation region
118
a
or
118
b.
SUMMARY OF THE INVENTION
In view of the above, a first object of the invention is to provide a method of forming shallow trench isolation which can make the control of chemical mechanical polishing easier, thereby to improve the uniformity of chemical mechanical polishing and to prevent the dishing effect.
A second object of the invention is to provide a method of forming shallow trench isolation which can make an insulating layer in a trench denser, thereby protecting the top corners of the trench from the formation of pits. Thus, the kink effect is prevented, increasing the performances of manufactured devices.
A third object of the invention is to provide a method of forming shallow trench isolation which can prevent microscratches.
To achieve the above-stated objects, the method of forming shallow trench isolation includes the following steps. First, a pad oxide layer, a first mask layer and a second mask layer having openings therein are formed on a substrate. Trenches are formed in the substrate by etching using the second mask layer as an etching mask. Then, a liner oxide layer is formed on the surfaces of the trenches by thermal oxidation. At the same time, protective oxide layers are formed on the exposed edges of the first mask. A buffer layer is formed over the substrate. Thereafter, an insulating layer is formed on the buffer layer, and completely fills the trenches. Next, the insulating layer is planarized by chemical mechanical polishing to form a remaining insulating layer which still covers the buffer layer. Part of the remaining insulating layer, part of the buffer layer and the second mask layer are removed by etch back. Subsequently, the first mask layer, the protective oxide layer and the pad oxide layer are removed in order.
Furthermore, the second mask layer can be omitted. In this case, the etching of STI is implemented by using a photoresist as an etching mask.


REFERENCES:
patent: 6020230 (2000-02-01), Wu
patent: 6074927 (2000-06-01), Kepler et al.
patent: 6180493 (2001-01-01), Chu

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