Integrated circuit device

Details Integrated circuit device Integrated circuit device

2007-10-16

2007-10-16

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000

Reexamination Certificate

active

11085149

ABSTRACT:
An LSI according to the present invention has a scan chain which comprises a plurality of SFFs between a buffer connected to an external pin and an internal circuit. During test mode, a test signal is inputted to the internal circuit of the LSI using the scan chain. In this case, a high-number-pins-test switch signal is inputted to an output buffer of a bidirectional pin of the external pins, set the bidirectional pin to output mode. Also, an output buffer is provided to an input pin, and the high-number-pins-test switch signal set the input pin to the output mode.

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patent: 1 291 662 (2003-03-01), None
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patent: 07-176618 (1995-07-01), None
patent: 2003-057309 (2003-02-01), None
European Search Report dated Jul. 18, 2005.

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