Integrated circuit bonding pads including conductive layers...

Details Integrated circuit bonding pads including conductive layers... Integrated circuit bonding pads including conductive layers...

2000-12-21

2003-04-22

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

C257S786000, C438S623000

Reexamination Certificate

active

06552438

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuits and methods of forming the same, and more particularly to bonding pads for integrated circuits and methods of forming the same.
BACKGROUND OF THE INVENTION
Integrated circuits, also referred to as “chips”, are widely used in consumer and commercial electronic products. As is well known to those having skill in the art, an integrated circuit generally includes a substrate such as a semiconductor substrate and an array of bonding pads on the substrate. The bonding pads provide an electrical connection from outside the integrated circuit to microelectronic circuits in the integrated circuit.
FIG. 1
is a schematic view of an integrated circuit package including a plurality of bonding pads. As shown in
FIG. 1
, an integrated circuit
100
, for example, a memory integrated circuit that includes a memory cell array portion
110
and a peripheral circuit portion
115
, may include a plurality of bonding pads
200
. The bonding pads
200
can act as a gate for a circuit terminal of the integrated circuit
100
and may be internally connected to an input/output (IO) buffer circuit in the peripheral circuit portion
115
.
As shown in
FIG. 1
, the integrated circuit
100
is attached to a lead frame
300
. Wire bonding or other conventional techniques may be used to connect a respective wire
320
to a bonding pad
200
and to an inner lead tip
310
of the lead frame
300
.
FIG. 2
is an enlarged top view of a bonding pad
200
of FIG.
1
.
FIG. 3
is a perspective view of the bonding pad of FIG.
2
.
FIG. 4
is a sectional view of the bonding pad taken along line IV-IV′ of
FIG. 2
, and
FIG. 5
is a sectional view of the bonding pad taken along line V-V′ of FIG.
2
.
In a conventional bonding pad structure as shown in
FIGS. 2 through 5
, independent conductive plugs
245
, such as tungsten plugs fill a plurality of via holes
240
in an interconnection dielectric layer
250
. The conductive plugs
245
electrically connect a lower aluminum interconnection layer
230
with an upper aluminum interconnection layer
260
. Reference numerals
210
,
220
, and
270
denote an integrated circuit substrate, an interdielectric layer, and a wire bonding region, respectively.
Unfortunately, the pad structure shown in
FIGS. 2 through 5
may have problems. For example, as shown in
FIGS. 4 and 5
, during sorting for separating good integrated circuits
100
from a wafer, cracks
330
may occur in the interconnection dielectric layer
250
due to the force of a probe pin of a tester that is applied to the wire bonding region
270
. The cracks
330
also may occur in the interconnection dielectric layer
250
due to stress caused by mechanical impact and pressure applied during bonding of a wire
320
in the wire bonding region
270
.
Cracks may occur because the upper aluminum interconnection layer
260
and the lower aluminum interconnection layer
230
which are relatively soft, may change in shape due to the stress applied during the sorting or wire bonding. However, the interconnection dielectric layer
250
which is relatively hard, does not readily change in shape. Thus, a stress higher than a predetermined value can cause a slip of unstable tungsten plugs
245
or cracks in the interconnection dielectric layer
250
. The cracks
330
may extend to the inside of the insulating layer
250
surrounding the tungsten plugs
245
as shown in FIG.
5
.
The cracks occurring in the interconnection dielectric layer
250
may generate an interconnection layer-open problem in which the upper and the lower interconnection layers
260
and
230
slip. Alternatively, a pad-open problem may be created in which contact between the wire
320
and the upper aluminum interconnection layer
260
becomes bad such that the wire
320
slips from the upper aluminum interconnection layer
260
.
FIG. 6
is a top view of another conventional bonding pad structure in which tungsten plugs
245
are formed only in a peripheral region around the outside of the central wire bonding region, to reduce the interconnection dielectric layer cracking and to reduce interconnection layer or wire slipping.
FIG. 7
is a sectional view of the bonding pad structure taken along line VII-VII′ of FIG.
6
. This bonding pad structure is disclosed in U.S. Pat. No. 5,248,903 and U.S. Pat. No. 5,502,337.
A bonding pad structure according to
FIGS. 6 and 7
and the above two patents, may reduce the cracks of the interconnection dielectric layer
250
. However, the number of the tungsten plugs
245
also is reduced, which can result in a weaker attachment between the tungsten plug
245
and the upper aluminum interconnection layer
260
. As a result, the interconnection layer-open phenomenon, in which the upper aluminum interconnection layer
260
is broken, may more easily occur during wire bonding. Also, since the number of plugs is reduced, which may reduce the area for contacting the upper aluminum interconnection layer
260
, an increase in the resistance R
S
and a reduction of current may result. Thus, sufficient current may not be supplied to a switching device in the integrated circuit, which may deteriorate the operation of the device.
SUMMARY OF THE INVENTION
Embodiments according to the present invention can provide bonding pads and methods that include arrays of unaligned spaced apart insulating islands. Pursuant to these embodiments, bonding pads for integrated circuits can include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer that extends therethrough such that sidewalls of the array of insulating islands are surrounded by the third continuous conductive layer.
In some embodiments, the array can include rows of unaligned spaced apart insulating islands and columns of unaligned spaced apart insulating islands. In other embodiments, the array of unaligned spaced apart insulating islands can also include a first insulating island having a first edge in a first direction and a second insulating island, adjacent to the first insulating island in the first direction having a second edge in the first direction that is unaligned with first edge.
In some embodiments, the bonding pad can further include a fourth continuous conductive layer between the third continuous conductive layer and the second conductive layer that is electrically connected to the third continuous conductive layer and to the second conductive layer. A second array of spaced apart insulating islands in the fourth continuous conductive layer extends therethrough such that sidewalls of the second array of insulating islands are surrounded by the fourth continuous conductive layer, wherein the second array of spaced apart insulating islands in unaligned with the first array of unaligned spaced apart insulating islands.
In some embodiments, the bonding pad can further include a metal bumper layer on a conductive layer and an upper bonding pad layer on the metal bumper layer that is configured to bond with a wire. In some embodiments, the metal bumper layer is tungsten. In still other embodiments, the metal bumper layer has a thickness of about 4000 Å. In other embodiments, the metal bumper layer and the upper bonding pad layer can be a single layer having a thickness in a range between about 12000 Å to 14000 Å. In some embodiments, the upper bonding pad layer is directly on the metal bumper layer.
In some embodiments, the metal bumper layer includes insulating islands that are located towards the outer edges of the metal bumper layer. In other embodiments, an inner region of the metal bumper layer is free of insulating islands.
In other embodiments, bonding pad structures according to the present invention can include first and second spaced apart conductive layers and a third continuous conductive layer between the first and second spaced apart conductive layers that is electrically

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