Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-06-24
2001-04-24
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S773000, C257S786000
Reexamination Certificate
active
06222270
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuits and methods of forming the same, and more particularly to bonding pads for integrated circuits and methods of forming the same.
BACKGROUND OF THE INVENTION
Integrated circuits, also referred to as “chips”, are widely used in consumer and commercial electronic products. As is well known to those having skill in the art, an integrated circuit generally includes a substrate such as a semiconductor substrate and an array of bonding pads on the substrate. The bonding pads provide an electrical connection from outside the integrated circuit to microelectronic circuits in the integrated circuit.
In the design of high performance integrated circuits, it is generally desirable to provide a low electrical resistance in the bonding pads. Unfortunately, as the integration density of integrated circuits continues to increase, more bonding pads may be needed in the integrated circuit, so that the area of each bonding pad may be lowered. Unfortunately, as the bonding pad becomes smaller, the resistance thereof may increase.
Moreover, as the integrated circuit device becomes more highly integrated, a step between the bonding pad and an insulating layer around the bonding pad may be produced. Reaction residue that is generated during a process of forming a contact hole on the insulating layer in order to expose the bonding pad, may become stacked at the edge of the step. The reaction residue may increase the contact resistance of the bonding pad.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved bonding pads for integrated circuits and methods of forming the same.
It is another object of the present invention to provide bonding pads for integrated circuits that can have low contact resistance, and methods of forming the same.
These and other objects are provided, according to the present invention, by multilayer bonding pads for integrated circuits that include first and second spaced apart conductive patterns and a dielectric layer therebetween. A closed conductive pattern is included in the dielectric layer that electrically connects the first and second spaced apart patterns. The closed conductive pattern encloses an inner portion of the dielectric layer and is enclosed by an outer portion of the dielectric layer. As is well known to those having skill in the art, a closed pattern is a curve that has no end points. The closed conductive pattern may be a circular, elliptical, polygonal or other conductive pattern.
A second closed conductive pattern may also be included in the inner portion of the dielectric layer, electrically connecting the first and second spaced apart conductive patterns. An open conductive pattern having end points, may also be included in the dielectric layer. The open conductive pattern may be included in the inner portion of the dielectric layer, in the outer portion of the dielectric layer or both.
A third conductive pattern may also be provided that is spaced apart from the second conductive pattern. A second dielectric layer is included between the second and third conductive patterns, and a fourth conductive pattern is included in the dielectric layer, electrically connecting the second and third spaced apart conductive patterns. The fourth conductive pattern may be an open conductive pattern.
Alternatively, the fourth conductive pattern may comprise a second closed conductive pattern in the second dielectric layer, electrically connecting the second and third spaced apart conductive patterns. The second closed conductive pattern encloses a second inner portion of the second dielectric layer and is enclosed by a second outer portion of the second dielectric layer. The second dielectric layer may also include additional open and closed conductive patterns therein, electrically connecting the second and third spaced apart conductive patterns.
In a preferred embodiment, the second and third conductive patterns are congruent to one another, and the closed conductive pattern and the second closed conductive pattern are of the same shape but of different sizes. In another preferred embodiment, the closed conductive pattern is an elliptical conductive pattern and the second closed conductive pattern is a polygonal closed conductive pattern.
By connecting conductive layer patterns with a closed conductive pattern in the dielectric layer, a step between an exposed region of the conductive pad and a dielectric layer covering an edge of the pad may be reduced. Reaction residue can therefore be reduced or prevented from being stacked on the step. Stacked residue can also be easily removed, to thereby lower the contact resistance of the pad.
Bonding pads according to the present invention may also be thought of as including first and second spaced apart conductive patterns and a dielectric layer therebetween, the dielectric layer including a closed via therein that extends between the first and second spaced apart conductive patterns. The closed via encloses an inner portion of the dielectric layer and is enclosed by an outer portion of the dielectric layer. A closed conductive pattern is provided in the closed via, electrically connecting the first and second spaced apart conductive patterns. The closed conductive pattern preferably fills the closed via. Various forms of closed conductive patterns and combinations with open conductive patterns may be provided, as was described above.
Bonding pads according to the present invention are preferably included on an integrated circuit substrate, to provide improved integrated circuits. Bonding pads according to the present invention may be formed by forming a dielectric layer on an integrated circuit substrate, the dielectric layer including the closed via therein that encloses an inner portion of the dielectric layer and is enclosed by an outer portion of the dielectric layer. A conductive pattern is formed in the closed via and on the dielectric layer opposite the substrate. The conductive pattern preferably fills the closed via. The steps of forming a dielectric layer and forming a conductive pattern may be repeatedly performed, to form a multilayer bonding pad on the integrated circuit substrate. The closed vias may have various shapes and may be combined with open vias as was described above. Accordingly, high performance bonding pads, integrated circuits and forming methods may thereby be provided.
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Clark Sheila V.
Myers Bigel Sibley & Sajovev
Samsung Electronics Co,. Ltd.
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