Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-12-13
2003-04-08
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
06546514
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of operating on a net-list describing an integrated circuit design, a method of generating test vectors to provide reduced numbers of miscompares between measured test results from a prototype integrated circuit design and simulated performance of the prototype integrated circuit design and a method of improving testability of an integrated circuit design.
BACKGROUND OF THE INVENTION
Integrated circuits have become increasingly complex, with the result that modeling and testing of integrated circuits has also become increasingly complex. In modeling and testing of integrated circuits and of new integrated circuit designs, it is increasingly difficult to discriminate between testing errors and performance errors as the intricacy of the integrated circuit being modeled or tested increases. Additionally, analysis of modeling results has become increasingly computationally intensive.
As a result, techniques for automating modeling and testing have been developed. One such technique, known as scan test, divides a proposed digital circuit design into scan paths using test logic that is to be built into the digital circuit, as is described, for example, in co-pending U.S. patent application Ser. No. 08/719,149, now U.S. Pat No. 5,938,782, which is assigned to the assignee of this application and which is hereby incorporated herein by reference. A scan path includes combinatorial logic and has an output signal that is solely a function of one input signal when appropriate test signals are applied to various parts of the digital circuit to isolate the scan path from other portions of the circuit and to capture input and output signals in flip flops that are included along the scan path.
Typically, each scan path consists of combinatorial logic, with a first flip-flop at or near a first end of the scan path latching a first signal and a second flip-flop at a second end of the scan path latching a second signal. The first and second signals may be input signals or output signals, depending on the tests being carried out and also depending on when the signals are sampled during a scan test. Multiple scan paths may be serially coupled together to form scan chains, where the output signal is a function of only one input signal. As a result, a number of circuit elements may be collectively tested by monitoring a limited number of signals, reducing the number of test signals that need to be supplied to the integrated circuit and also the number of output signals that must be analyzed in order to assess functionality of the circuit.
An automatic test pattern generator (ATPG) analyzes a description of the logic functions in the integrated circuit, known as a net-list, and from the net-list synthesizes a series of input signals known as test vectors. The test vectors are input to a corresponding series of scan chains when the circuit being tested is set to the test mode of operation. The ATPG also synthesizes a series of simulated output signals. Measured scan output signals are compared with their expected values from simulation to determine which output signals correspond to their expected values and which output signals are erroneous, i.e., have values that do not correspond with their expected values. Erroneous output signals from the scan chains may result from a variety of causes.
A first potential cause may be a malfunction of the combinatorial circuitry in the scan path. This type of malfunction is what the scan architecture is intended to capture and identify.
A second potential cause may be a malfunction of the flip-flop that is intended to capture the output signal from the scan path. This may be due, for example, to improper clocking or reset behavior of the scan flip-flop, which may be caused by noise or spikes in the clock signal applied to the flip-flop. This may also be due to latching of false data by the flip-flop, which may be caused by a race condition or clock skew. These kinds of error signals are the result of problems occurring during data capture by the flip-flops.
A third potential cause of error can be clock skew or missing clock pulses, giving rise to resetting of flip-flops, among other things. When these occur in the scan chain, they result in unexpected resetting of one or more scan flip-flops following data capture, destroying the scan data. Erroneous gating or defective multiplexer operation in the prototype integrated circuit design may also result in corruption of the output signal from the prototype integrated circuit. These kinds of problems are associated with defects in shifting data through the prototype integrated circuit.
However, when one or more defects of one or more types are present, the output signals obtained in this manner are not easily interpreted. Further, it may be extremely difficult to discriminate between errors due to malfunction of the circuitry under test and errors due to problems that are only associated with the test mode of operation, such as problems occurring during the data capture and data shift operations. These latter problems are not indicative of defects in the circuitry being tested.
Typically, output data captured in response to application of a test vector from the ATPG are arranged in text files. Examination of the output data coupled with detailed parsing of the data flow through the integrated circuit being tested is needed to trace propagation of test signals through the circuit being tested in order to determine where the error or errors occurred during the course of the test. This process is extremely labor intensive and frequently is also subject to errors in interpretation.
In effectuating a new integrated circuit design, a series of photomasks are designed. When these masks have been made, they are used to build a prototype of the new integrated circuit design. Typically, the ATPG is used to generate test vectors after the photomasks have been designed and the design has been given to the photomask facilities. This happens because the test vectors typically are not needed for testing of the prototype integrated circuit until several weeks after the photomask has been designed, and because there is no reason, from a marketing point of view, to generate the test vectors earlier.
One problem with this approach is that when a malfunction of the new integrated circuit design is found during the course of generating the test vectors, the consequences may be severe. These may require the design team to mask (or ignore) one or more outputs from the new integrated circuit prototype, which results in dramatically decreased fault coverage. In severe cases, these malfunctions may cause the design team to cancel the photomask design and to generate a revised mask design, or to order new photomasks and to build a second prototype integrated circuit from the new photomasks.
When problems are due to unexpected behavior, such as resetting of a flip-flop in the scan chain, a large number of miscompares may be noted between the expected or simulated results and the results that are measured from a prototype of a new integrated circuit design. What is needed is a way to reduce the number of miscompares between expected test results and measured test results from a prototype integrated circuit design with less reduction of test coverage than occurs when an output is masked.
SUMMARY OF THE INVENTION
In one aspect, the present invention includes a method of operating on a net-list describing an integrated circuit design for use with an automated test pattern generator for testing an integrated circuit built using the design. The method includes replacing a defective portion of the design in test mode with a substitute circuit to reduce testing impact of the defective portion by identifying a first defective portion of the integrated circuit design in the net-list, determining conditions under which the first defective portion is likely to malfunction and replacing the first defective portion in the net-list with another first portion that provides unknown output signals represe
Arnould Patrick
Hayem Frederic
Ton David
Zawilski Peter
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