Integrated circuit

Details Integrated circuit Integrated circuit

2005-04-07

2008-03-18

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000, C714S744000

Reexamination Certificate

active

07346822

ABSTRACT:
An integrated circuit including test circuitry, the test circuitry including a counter for counting clock signals and having an output for providing a control signal. The counter being arranged to have an internal state, and the counter being arranged to change the control signal on the internal state of counter reaching a predetermined value.

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Hirabayashi O., et al. “DFT Techniques For Wafer-Level At-Speed Testing of High-Speed SRAMs” Proceedings International Test Conference 2002. ITC 2002. Baltimore, MD, Oct. 7-10, 2002, International Test Conference, New York, NY: IEEE US, Oct. 7, 2002, pp. 164-169, XP010609738.

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