Integrated circuit

Details Integrated circuit Integrated circuit

2007-04-10

2007-04-10

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S120000

Reexamination Certificate

active

11086655

ABSTRACT:
An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.

REFERENCES:
patent: 4161691 (1979-07-01), Vermeers
patent: 4460867 (1984-07-01), Fleissner
patent: 4639665 (1987-01-01), Gary
patent: 4961049 (1990-10-01), Ghislanzoni
patent: 5146156 (1992-09-01), Marcel
patent: 5581204 (1996-12-01), Olsen
patent: 2003/0221149 (2003-11-01), Vollrath

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