Integrated capacitor bottom electrode with etch stop layer

Details Integrated capacitor bottom electrode with etch stop layer Integrated capacitor bottom electrode with etch stop layer

1997-08-21

2000-04-11

Wojciechowicz, Edward

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438255, 438256, 438398, 438399, 257296, 257301, 257309, 257532, H01L 2972

Patent

active

060487631

ABSTRACT:
A process of forming a capacitor on a surface of a wafer having one or more word lines and an active area adjacent the word lines. The word lines are isolated from the active areas by isolation spacers. The process comprises the steps of forming a multilayer structure over the word lines and the active area, selectively removing a portion of the multilayer structure to expose active area and to form a capacitor container region above the active area and sequentially depositing the bottom electrode, the cell dielectric and the upper electrode of the capacitor. The multilayer structure comprises a conformal etch stop layer, a sacrificial layer and a mask layer. The etch stop layer protects the active area and word line spacers during a selective etch of the sacrificial layer, and the etch stop layer may then be removed with minimal damage to the gate electrode spacers. In the preferred embodiment, the process requires only two masking steps to form a fully isolated, high-surface area capacitor for a DRAM cell.

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