Integrated approach for controlling top dielectric loss...

Details Integrated approach for controlling top dielectric loss... Integrated approach for controlling top dielectric loss...

2002-05-02

2002-12-24

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S592000, C438S595000

Reexamination Certificate

active

06498067

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a composite insulator spacer on the sides of a metal oxide semiconductor field effect transistor (MOSFET), gate structure.
(2) Description of Prior Art
The use of salicide (self-aligned metal silicide), processing, enabling a metal silicide layer to be selectively formed only on gate and source/drain regions, has allowed increased performance of MOSFET structures to be realized. The low resistivity metal silicide layers, such as titanium silicide, cobalt silicide, tantalum silicide or tungsten silicide lower word line resistance when formed on underlying polysilicon gate structures. Salicide processing is made possible by the presence of an insulator spacer located on the sides of a gate structure, allowing the deposited metal used for salicide formation, to remain unreacted during an anneal procedure used to form metal silicide on exposed silicon regions, such as word line and source/drain surfaces. The unreacted metal, located on the surface of the insulator spacer, is then selectively removed via wet etch procedures. Therefore the integrity of the insulator spacer is critical in preventing gate to substrate leakage and shorts.
To improve the integrity of the insulator spacer, and to reduce the risk of gate to substrate failures occurring during salicide processing, composite insulator spacers have been employed. The composite insulator spacer, usually comprised with an underlying silicon oxide layer, and an overlying silicon nitride layer, can better survive the rigorous salicide process regarding metal deposition, annealing, and removal of unreacted metal, when compared to non-composite insulator spacers. The formation of composite insulator spacers however can result in removal of a top portion of the composite spacer during a spacer over etch cycle, used to insure complete spacer formation in regions in which poor insulator thickness uniformity existed. The removal of the top portion of the composite insulator spacer exposes a portion of the sides of a gate structure thus allowing metal silicide to be formed on this region, which in turn reduces the distance between the gate and source/drain region, thus reducing the distance unwanted salicide stringers, or ribbons, formed during the salicide process on the truncated spacer, have to traverse to result in the unwanted phenomena of gate to substrate leakage or shorts.
The present invention will describe a process in which re-formation of sidewall insulator is used post-composite insulator spacer definition, to reduce the risk of salicide bridging resulting from a composite insulator spacer truncated, or with a top portion of the composite insulator spacer removed, during the spacer formation. Prior art, such as Thomas, in U.S. Pat. No. 6,242,354, as well as Huang et al, in U.S. Pat. No. 6,218,275, describe methods of forming insulator spacers, however these prior arts do not describe the novel procedures now described in the present invention in which re-formation of portions of insulator spacer, possibly removed during an initial spacer formation procedure, is accomplished.
SUMMARY OF THE INVENTION
It is an object of this invention to selectively form metal silicide layers on a gate structure and on a source/drain region of a MOSFET device.
It is another object of this invention to form a composite insulator spacer on the sides of the MOSFET gate structure, to allow the selective metal silicide, or silicide formation procedure to be practised.
It is still another object of this invention to form additional insulator spacer shapes on the sides of the composite insulator spacer, or on the sides of portions of gate structure, exposed as a result of removal of a top portion of the composite insulator during a dry etch over etch cycle, used as part of the composite insulator spacer definition procedure.
In accordance with the present invention a method of re-establishing insulator spacer shapes on the sides a gate structure, where portions of the initial composite insulator spacer were removed during a dry etch over etch cycle, used as part of the composite insulator spacer definition procedure, is described. After formation of a gate structure on an underlying gate insulator layer, a lightly doped source/drain region is formed in a region of the semiconductor substrate not covered by the gate structure. A thin first insulator layer is deposited, followed by deposition of a second insulator layer. A first anisotropic, reactive ion etching (RAE) procedure is then performed to the second insulator layer, defining a second insulator spacer shape, with the RIE procedure selectively terminating at the appearance of the top surface of the thin first insulator layer located on the top surface of the gate structure. The first anisotopic RIE procedure is then continued to insure complete removal of the second insulator layer in regions of thickness un-uniformity, or in regions in which the second insulator layer formed in crevices or micro-trenches in the semiconductor substrate, located near a shallow trench isolation shape. The over etch procedure results in removal of a top portion of the second insulator component of the composite insulator spacer, exposing a portion of the sides of the gate structure or a portion of the thin first insulator layer still located on the sides of the gate structure. A third insulator layer is next deposited followed by a second anisotropic RIE procedure, employed to again selectively terminate at the appearance of the thin, first insulator layer located on the top surface of the gate structure. This results in formation of third insulator shapes located on the sides of the thin, first insulator layer, exposed during the first anisotropic RIE procedure, in addition to resulting in third insulator shapes located on the bottom portion of the truncated second insulator shape. After formation of a heavily doped source drain region, portions of the thin, first insulator layer, located on the top surfaces of the gate structure and on the surface of the heavily doped source/drain region, are selectively removed. A metal layer is next deposited and subjected to an anneal resulting in metal silicide formation on the top surface of silicon regions. Unreacted metal, located on the composite insulator layer, now comprised of an underlying, thin first insulator layer, a truncated second insulator shape, and third insulator shapes located on the exposed surface of the thin, first insulator layer, and on the surface of the truncated second insulator shape, is selectively removed via wet etch procedures.


REFERENCES:
patent: 5920783 (1999-07-01), Tseng et al.
patent: 5994192 (1999-11-01), Chen
patent: 5994227 (1999-11-01), Matsuo et al.
patent: 6165913 (2000-12-01), Lin et al.
patent: 6190961 (2001-02-01), Lam et al.
patent: 6218275 (2001-04-01), Huang et al.
patent: 6242354 (2001-06-01), Thomas
patent: 6440875 (2002-08-01), Chan et al.
patent: 6455383 (2002-09-01), Wu

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