Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
1999-09-21
2001-11-20
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S190000, C365S189050, C365S189110
Reexamination Certificate
active
06320806
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an input/output sense amplifier of a semiconductor memory device.
2. Description of the Related Art
In general, a dynamic random access memory (DRAM) includes a plurality of memory cell arrays, each divided into a plurality of sub-arrays. Each memory cell included in a memory cell sub-array is randomly accessed to store data therein and to output the data stored therein.
FIG. 1
shows a conventional semiconductor memory device. When writing data to a memory, data DI is inputted to an input buffer
18
and latched by an input latch
20
. After global input/output lines GIO and /GIO are precharged by a precharge circuit
24
, the latched data is applied to the global input/output lines GIO and /GIO via an input driver
22
. Here, one memory cell within a memory cell array
10
is selected by a word line WL activated by a row decoder
14
and a column selection line CSL activated by a column decoder
16
, and the data on the global input/output lines GIO and /GIO are written to the selected memory cell via a local input/output line LIO.
Also, when reading data written to the memory device, a specific word line WL is activated by row decoder
14
. Then, the cells connected to word line WL transfer data to corresponding bit lines and bit line sense amplifiers (not shown) sense the signals on the bit lines. Data from a bit line among the plurality of bit lines is selected by column selection line CSL activated by column decoder
16
, and transferred via local input/output line LIO to global input/output lines GIO and /GIO that were precharged by precharge circuit
24
. The data on global input/output lines GIO and /GIO are amplified by an input/output (I/O) sense amplifier
26
, and then outputted via an output buffer
28
.
As described above, when writing data to the memory or reading the data from the memory device, global input/output lines GIO and /GIO are precharged. Then, data is written to or read from precharged global input/output lines GIO and /GIO. In particular, when writing data in the conventional memory device, the precharge level of global input/output lines GIO and /GIO is set to be the same as the precharge level when the data is read from the memory device.
FIG. 2
is a graph showing the change in potential over time on global input/output lines GIO and /GIO in the semiconductor memory device of FIG.
1
. Writing occurs during intervals T
12
and T
14
and reading occurs during interval T
16
. Before writing or reading, global input/output lines GIO and /GIO are precharged during intervals T
13
and T
15
. As shown in
FIG. 2
, the precharge levels of global input/output lines GIO and /GIO are equal to 1.45V in intervals T
14
and T
16
.
Also, in order to reduce power consumption in memory devices, power supply voltages for such devices have decreased. As the power supply voltages have decreased, the precharge levels of the input/output lines have correspondingly decreased. However, if the precharge level is too low, a semiconductor device cannot operate normally. Such abnormal operation is more serious when reading from the memory device than when writing to the memory device. In particular, when the precharge level is low, an input/output sense amplifier does not operate normally, making it difficult to obtain the correct data from the memory device.
SUMMARY OF THE INVENTION
To solve the above problems, embodiments of the present invention provide a precharge circuit of a semiconductor memory device which operates at a comparatively low power supply voltage and is capable of precharging input/output lines to a sufficiently high voltage during a reading operation.
In accordance with one embodiment of the invention, a semiconductor memory device includes: first and second data input/output lines; a memory cell array including a plurality of memory cells, each storing data and accessed by word lines and paired bit lines; a row decoder for receiving a row address and decoding the row address to activate one of the word lines; a column decoder for receiving a column address and decoding the column address to activate one of the column selection lines, thereby connecting a pair of bit lines to the first and second data input/output lines; an input buffer for receiving data to be written; an input driver that varies the voltages of the first and second data input/output lines according to the data to be written; an input/output line sense amplifier for sensing the voltages of the first and second data input/output lines and amplifying the voltages during a read operation; an output buffer for buffering the outputs; of the input/output line sense amplifier to output read data; and a precharge circuit for precharging the first and second data input/output lines before the writing and read operations.
REFERENCES:
patent: 5862090 (1999-01-01), Numata et al.
patent: 5973972 (1999-10-01), Kwon et al.
patent: 7-037387 (1995-02-01), None
Heid David W.
Lam David
Nelms David
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
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