Input buffer having a compensation circuit for stabilizing the o

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

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326 34, 326121, 327543, 327546, H03K 1714, H03K 190948, H03K 19003

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active

054081912

ABSTRACT:
An input buffer particularly suitable for a semiconductor device includes a CMOS inverter for buffering an input signal which varies between first and second logic levels and producing an output signal at an output node thereof which is the logical inverse of the input signal, and a compensation circuit for compensating the output signal for fluctuations thereof which are due to fluctuations of a supply voltage. The CMOS inverter preferably includes a pull-up MOS transistor having a gate, a first electrode coupled to a supply voltage, and a second electrode, and a pull-down MOS transistor having a gate, a first electrode coupled to a reference voltage, and a second electrode. The compensation circuit preferably includes a compensation MOS transistor having a gate, a first electrode coupled to the second electrode of the pull-up MOS transistor, and a second electrode coupled to the second electrode of the pull-down MOS transistor, with the output node being located intermediate the second electrode of the compensation MOS transistor and the second electrode of the pull-down MOS transistor. The compensation circuit further includes a compensation control circuit coupled to the supply voltage for controllably varying the electrical resistance of the channel of the compensation MOS transistor in such a manner as to minimize fluctuations of the voltage level of the output signal due to fluctuations of the supply voltage.

REFERENCES:
patent: 4763021 (1988-08-01), Stickel
patent: 5051630 (1991-09-01), Kogan et al.
patent: 5073726 (1991-12-01), Kato et al.
patent: 5136182 (1992-08-01), Fawal
patent: 5278460 (1994-01-01), Casper

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