Input buffer circuit

Electronic digital logic circuitry – Interface – Current driving

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Details

326 34, H03K 190175

Patent

active

057449821

ABSTRACT:
A CMOS inverter has two p-channel FETs connected in series between V.sub.DD and the inverter output node, an upper FET connected to V.sub.DD and a lower FET connected to the output node. The gate of a upper FET and the gate of the inverter n-channel FET are connected to the circuit input through a series FET that protects the gate oxide of these FETs by turning off if a high voltage appears at the circuit input. The circuit is useful as a buffer that receives binary voltages that may be higher than the binary voltages of the circuits of the same chip. The gate of the upper p-channel FET is connected to the input and turns off fully to block a leakage current that would otherwise flow when the n-channel FET is turned on but the lower p-channel FET is left partly conducting by the voltage drop across the series FET. The gate oxide of the upper FET is protected because the partly conducting lower p-channel FET is turned off sufficiently to impede the charging current of the capacitor formed in part by the gate oxide.

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