Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-12-14
2001-04-10
Wiley, David A. (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
Reexamination Certificate
active
06216194
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an information processing unit having a plurality of shared buses and an adaptor (optional board) connected to the shared buses, and particularly to an information processing unit that prevents the shared buses from falling into bottleneck when data is transferred through the buses, thereby enabling the data transfer to be efficiently conducted.
A known example of the efficient data transmission is disclosed in JP-A-7-141285. In this example, a plurality of adaptors are connected to two shared buses, and select an unused bus in order for data to be transferred through the bus. In the reference JP-A-7-141285, when one of a plurality of adaptors that use two shared buses at a time requests for data transfer, the other ones wait for at least one of the two shared buses to become unused.
Another example is disclosed in JP-A-5-204822. In this example, a processor is used to control two shared buses independently, thereby enabling its read cycle and write cycle operations to be made in parallel, that is, data can be efficiently transferred through the shared buses. In this technique, a plurality of modules to be controlled by the processor are connected to the shared buses, and operated to read or write, transferring data to each other. However, the same module does not make read and write operations at a time.
In addition, efficient data transfer can be made by use of fast clock or by expanding data bus. As this bus controlling method, there are known, for example, a bus mediation circuit disclosed in JP-A-7-210498, and a cache coherence control method using an information processing unit described in JP-A-9-198307.
In these conventional method, however, when fast clock is used, the pattern design and electromagnetic wave leaking countermeasure need high-order skill because of high frequency, and are thus troublesome to make. Even when the width of data to be transferred is expanded, data on the shared bus is transferred in one direction during a certain period of time, that is, data cannot be transferred in both directions at a time.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an information processing unit capable of transferring data in both directions at a time without use of fast clock.
According to the invention, there is provided an information processing unit having a bus controller and at least one adaptor that can control two or more separated shared buses to which a plurality of adaptors can be connected, wherein when the adaptor connected to one shared bus is needed to transfer more data than the capability of the shared bus, the bus controller and adaptor are provided with functions capable of separately controlling the first and second shared buses at a time in order to improve the performance of the shared bus.
The bus controller is notified by an upper MPU about whether or not the same adaptor is connected to both separated shared buses.
The adaptor and the bus controller, when controlling one of the separated shared buses, make it serve as an up bus exclusive for sending data from the adaptor to bus controller. When controlling the other bus, they make it serve as a down bus exclusive for sending data from the bus controller to adaptor.
In this case, the adaptor and the bus controller control the separated shared buses to serve as up data bus and down data bus on the basis of the numbers attached to the separated shared buses.
Since the adaptor is thus arranged to connect to two or more shared buses, the data transfer capability of the information processing unit can be improved.
According to the invention, two or more separated shared buses can be controlled independently by the bus controller and adaptor in the information processing unit that has a plurality of adaptors connected to the shared buses as described above. When data is transferred between the bus controller and the adaptor, the adaptor controls separately one shared bus for sending data to the bus controller, and the other different bus for accepting data from the bus controller, while the bus controller and adaptor use the two different shared buses at a time. Therefore, data transfer between the adaptor and bus controller can be made in both directions at a time without use of fast clock.
REFERENCES:
patent: 5495583 (1996-02-01), Townsend et al.
patent: 5572688 (1996-11-01), Sytwu
patent: 5740378 (1998-04-01), Rehl et al.
patent: 5768612 (1998-06-01), Nelson
patent: 5812801 (1998-09-01), Saperstein et al.
patent: 5-204822 (1993-08-01), None
patent: 7-141285 (1995-06-01), None
patent: 7-210498 (1995-08-01), None
patent: 9-198307 (1997-07-01), None
Aoyama Takaharu
Katoh Tsuyoshi
Matsuyama Nobuhito
Shioda Hirokatsu
Sugai Kazuo
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Wiley David A.
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