Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
2006-07-18
2006-07-18
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S311000, C438S341000, C438S478000, C438S481000, C438S607000, C438S933000, C257S779000, C257S780000
Reexamination Certificate
active
07078353
ABSTRACT:
The invention provides a method of producing a structure of a thin layer of semiconductor material on a support substrate. The thin layer is obtained from a donor substrate and includes an upper layer of semiconductor material. The method includes forming on the upper layer a bonding layer of a material that accepts diffusion from an element of the material of the upper layer, bonding the donor substrate from the side on which the bonding layer is formed on the upper layer to the support substrate, and diffusing the element from the upper layer into the bonding layer to homogenize the concentration of the element in the bonding layer and the upper layer. The result is that the thin layer of the structure is joined by the bonding layer to the upper layer.
REFERENCES:
patent: 6573126 (2003-06-01), Cheng et al.
patent: 6703144 (2004-03-01), Fitzgerald
patent: 6713326 (2004-03-01), Cheng et al.
patent: 6723541 (2004-04-01), Sugii et al.
patent: 6724008 (2004-04-01), Fitzergald
patent: 6737670 (2004-05-01), Cheng et al.
patent: 6746902 (2004-06-01), Maa et al.
patent: 6780796 (2004-08-01), Maa et al.
patent: 6793731 (2004-09-01), Hsu et al.
patent: 6841457 (2005-01-01), Bedell et al.
patent: 2001/0003269 (2001-06-01), WU et al.
patent: 2002/0014692 (2002-02-01), Yamada et al.
patent: 2002/0030227 (2002-03-01), Bulsara et al.
patent: 2002/0146892 (2002-10-01), Notsu et al.
patent: 2003/0013305 (2003-01-01), Sugii et al.
patent: 2003/0155568 (2003-08-01), Cheng et al.
patent: 2003/0168654 (2003-09-01), Cheng et al.
patent: 2004/0192067 (2004-09-01), Ghyselen et al.
patent: 2005/0009288 (2005-01-01), Cheng et al.
patent: 0 371 862 (1990-06-01), None
patent: 1 248 294 (2002-10-01), None
patent: WO 99/53539 (1999-10-01), None
patent: WO 01/54202 (2001-07-01), None
patent: WO 02/33746 (2002-04-01), None
T.A. Langdo et al., “Preparation of Novel SiGe-Free Strained Si on Insulator Substrates”, 2002 IEEE International SOI Conference, pp. 211-212 (2002).
J.P. Collinge, :“Silicon-on-insulator technology”, Materials to VLSI, 2nd Edition, Kluwer Academic Publisher, pp. 50-51.
T.A. Langdo et al., “SiGe-free strained Si on insulator by wafer bonding and layer transfer” Applied Physics Letters, vol. 82, No. 24, pp. 4256-4528 (2003).
Aulnette Cécile
Cayrefourcq Ian
Daval Nicolas
Ghyselen Bruno
Rayssac Oliver
Pham Long
Rao Shrinivas H.
S.O.I.Tec Silicon on Insulator Technologies S.A.
Winston & Strawn LLP
LandOfFree
Indirect bonding with disappearance of bonding layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Indirect bonding with disappearance of bonding layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Indirect bonding with disappearance of bonding layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3608404