Increasing self-aligned contact areas in integrated circuits...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S299000, C257SE21435, C257SE21632

Reexamination Certificate

active

07323377

ABSTRACT:
In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material over the stepped portion; (ii) forming a source/drain region by performing ion implantation through a portion of the first liner over the source/drain region; (iii) replacing the disposable spacer material with a second liner formed over the first liner after forming the source/drain region; (iv) forming a pre-metal dielectric over the second liner; and (v) forming a self-aligned contact through the pre-metal dielectric. Among other advantages, the method allows for an increased contact area for a self-aligned contact.

REFERENCES:
patent: 4885617 (1989-12-01), Mazure-Espejo et al.
patent: 5102816 (1992-04-01), Manukonda et al.
patent: 5798278 (1998-08-01), Chan et al.
patent: 5804846 (1998-09-01), Fuller
patent: 5905293 (1999-05-01), Jeng et al.
patent: 6027961 (2000-02-01), Maiti et al.
patent: 6228731 (2001-05-01), Liaw et al.
patent: 6670227 (2003-12-01), Thio et al.
patent: 6724057 (2004-04-01), Ibara et al.
patent: 6746926 (2004-06-01), Yu
patent: 2002/0197786 (2002-12-01), Cho et al.
patent: 2003/0087517 (2003-05-01), Lee
John Gumpher, et al. “Characterization of Low-Temperature Silicon Nitride LPCVD from Bis (tertiary-butylamino) silane and Ammonia” Mar. 26, 2004, pp. G353-G359, Journal of the Electrochemical Society.
Chang, Hsiao-Yung “Modeling and Simulation of a Tungten Chemical Vapor Deposition Reactor” Aug. 1, 2000 (Abstract) pp. 1-154, University of Maryland, College Park.
Sato, Yasuhiro, et al. “300-kilo gate sea-of-gate arrays . . . ” Aug. 10, 1998; accepted Sep. 17, 1998, Abstract [online] Japanese Journal of Applied Physics; [retrieved on Feb. 12, 2002] Retrieved from Online Journal Publishing Service (OJPS).
Chang, Kow-Ming, et al. “Characteristics of Selective Chemical Vapor Deposition of Tungsten on Aluminum with a Vapor Phase Precleaning Technology” Jan. 1997, pp. 251-258, vol. 144, No. 1; Electrochemical Society, Inc., Hsinchu, Taiwan.
Van Der Putte, P. et al. “Growth of selective tungsten films on self-aligned CoSi2 by low pressure chemical vapor deposition” Aug. 1996, accepted Oct. 1996; pp. 1723-1725, vol. 49, No. 25; Applied Physics Lett. Signetics Corporation, Sunnyvale, California.
Kosugi, Toshihiko, et al. “Novel SI Surface Cleaning Technology with Plasma Hydrogenation and Its Application to Selective CVD-W Clad Layer Formation” 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 41-42; Atsugi, Kanagawa, Japan.
Takahashi, Mitsutoshi, et al. “Si Consumption In Selective Chemical Vapor Deposition of Tungsten Using SiH4 Reduction of WF6” Jun. 16, 2000; revised manuscript Oct. 30, 2000; pp. G229-G231, Journal of the Electrochemical Society; Atsugi, Kanagawa, Japan.
Takahashi, Mitsutoshi, et al. “Fully Depleted 20-nm SOI CMOSFETs with W-Clad Gate/Source/Drain Layers” Jul. 2001, pp. 1380-1385, vol. 48 No. 7, IEEE Transactions on Electron Devices.
Chang, Kow-Ming, et al. “Interface Characteristics of Selective Tungsten on Silicon Using a New Pretreatment Technology for ULSI Application” May 1997, pp. 738-743, vol. 44 No. 5, IEEE Transactions on Electron Devices.
B.W. Shen, et al. “Diffusion barrier properties of thin selective chemical vapor deposited tungsten films”, 1996, pp. 1369-1376, vol. 4 No. 6, J. Vac. Sci. Technol.; Texas Instruments, Dallas, Texas.
Wen-Kuan Yeh, et al. “Effect of surface pretreatment of submicron contact hole on selective tungsten chemical vapor deposition” 1996, pp. 167-173, vol. 14 No. 1, J. Vac. Sci. Technol.; Hsinchu Taiwan, Republic of China.
M. Sekine, et al, “Self-Aligned Tungsten Strapped Source/Drain and Gate Technology Realizing the Lowest Sheet Resistance for Sub-quarter Micron CMOS” 1994, pp. 493-496, IEEE; NEC Corp., Kanagawa, Japan.
Blewer, Robert S “Progress in LPCVD Tungsten for Advanced Microelectronics Applications”, Nov. 1986, pp. 177-126; Albuquerque, New Mexico.
Sato, Yasuhiro, et al. “300-kilo-Gate Sea-of-Gate Type Gate Arrays Fabricated Using 0.25-um-Gate Ultra-Thin-Film Fully Depleted Complementary Metal-Oxide-Semiconductor Separation by IMplanted OXygen Technology with Tungsten-Covered Source and Drain”, 1998, pp. 5875-5879, vol. 37 No. 11, Japanese Journal of Applied Physics; Japan.
Kobayashi, Nobuyoshi, et al. “Study on mechanism of selective chemical vapor deposition of tungsten using in situ infrared spectroscopy and Auger electron spectroscopy”, 1991, pp. 1013-1019, vol. 69, No. 2, Journal of Applied Physics; Japan.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Increasing self-aligned contact areas in integrated circuits... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Increasing self-aligned contact areas in integrated circuits..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Increasing self-aligned contact areas in integrated circuits... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2761248

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.