Increased effective transistor width using double sidewall space

Details Increased effective transistor width using double sidewall space Increased effective transistor width using double sidewall space

1998-04-30

2000-08-01

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438297, 438298, 438424, 438425, H01L 21336, H01L 2176

Patent

active

060966122

ABSTRACT:
A structure and a method for fabricating integrated circuits are disclosed in which narrow trench isolation structures (36) are formed between active regions (38) of an integrated circuit (10). A silicon nitride layer is deposited, patterned and etched to provide nitride mask (16) having spaces (20) which are preferably no larger than the minimum photolithography spacing limits. Single sidewall oxide spacers (24) are formed on the sidewalls of the nitride mask by depositing a conformal coating of oxide and then applying an anisotropic etch, leaving the oxide spacers (24) of approximately 100 to 500 Angstroms thickness on the sidewalls of the nitride mask (16). Isolation trenches (26) are etched into a silicon substrate (12) in the spaces between adjacent ones of the oxide spacers (24). The oxide spacers (24) are then removed without removing the nitride mask (16), leaving ledges, or shelf regions (28), of the substrate (12) in the spaces between the trenches (26) and the nitride mask (16). Channel stops (30) are implanted into the shelf regions (28). Oxide plugs (34) are formed within the trenches (26). Double sidewall spacers, such as nitride spacers (114) and oxide spacers (118), may be used to reduce the width of the trench isolation structure (140). The edges (66) of the isolation trench (60) may also be rounded.

REFERENCES:
patent: H204 (1987-02-01), Oh et al.
patent: 4276099 (1981-06-01), Keen et al.
patent: 4570325 (1986-02-01), Higuchi
patent: 5068202 (1991-11-01), Crotti et al.
patent: 5385853 (1995-01-01), Mohammad
patent: 5385861 (1995-01-01), Bashir et al.
patent: 5387538 (1995-02-01), Moslehi
patent: 5395790 (1995-03-01), Lur
patent: 5399520 (1995-03-01), Jang
patent: 5407837 (1995-04-01), Eklund
patent: 5411913 (1995-05-01), Bashir et al.
patent: 5424240 (1995-06-01), Han
patent: 5436190 (1995-07-01), Yang et al.
patent: 5453395 (1995-09-01), Lur
patent: 5472902 (1995-12-01), Lur
patent: 5474953 (1995-12-01), Shimizu et al.
patent: 5492853 (1996-02-01), Jeng et al.
patent: 5518950 (1996-05-01), Ibok et al.
patent: 5599722 (1997-02-01), Sugisaka et al.
patent: 5674775 (1997-10-01), Ho et al.
patent: 5753561 (1998-05-01), Lee et al.
patent: 5795811 (1998-08-01), Kim et al.
patent: 5874317 (1999-02-01), Stolmeijer
Tai-su Park, Yui Gyun Shi, Han Sin Lee, Moon Han Park, Sang Dong Kwon, Ho Kyu Kang, Young Bum Koh and Moon Yong Lee, "Correlation Between Gate Oxide Reliability and the Profile of the Trench Top Corner in Shallow Trench Isolation (STI)", IEDM 96-747, pp. 29.6.1-29.6.4.

Affiliated with

Also associated with

Rating

Increased effective transistor width using double sidewall space does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Increased effective transistor width using double sidewall space, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Increased effective transistor width using double sidewall space will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-663190