Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-26
2003-09-16
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S248000, C438S255000, C438S386000, C438S391000, C438S398000, C438S964000
Reexamination Certificate
active
06620675
ABSTRACT:
DETAILED DESCRIPTION OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of trench capacitors for integrated circuits; more specifically, it relates to trench capacitors having an increased plate area and methods of fabricating said trench capacitors.
2. Background of the Invention
Dynamic random access memories (DRAM) are widely used in computer technology. Typically, the DRAM cells are used to store data in the form of bits. DRAMs store bits as charge (or the absence of charge) on a capacitor. Since the charge can leak off, DRAMs must be periodically refreshed. Refreshing consumes power and time. Additionally, as DRAM performance has increased cell size, and horizontal capacitor size has decreased. Decreasing the size of the capacitor results in less charge being stored, making the cell more difficult to read as well as more sensitive to leakage.
One type of capacitor used for DRAMs is a trench capacitor. A trench capacitor is formed by forming a trench in a silicon substrate, lining the sidewalls of the trench with a dielectric and filling the trench with a conductive material. The substrate acts as one plate of the capacitor and the conductive fill as the second plate. The capacitance of a trench capacitor is a function of the dielectric thickness and the surface area of the trench sidewalls and bottom, which define the plate area as given by C=Î&mgr;A/d, where C is the capacitance, Î&mgr; is the dielectric constant of the dielectric layer, d is the thickness of the dielectric layer and A is the surface area of the plates.
Capacitance of a trench capacitor may be increased in several ways. First, the dielectric layer may be made thinner, but leakage becomes a concern. Second, the dielectric may be selected to have a high dielectric constant, but such exotic materials are hard to control and incorporate into DRAM technology. Third, the area of the plates may be increased. Since the area of the plates has been decreasing by reducing horizontal dimension of the trench capacitor, increasing the vertical depth of the trench capacitor has indeed been done. However, there are technology limits as to how deep a trench can be etched in silicon before vertical etch depth does not increase significantly with increased etch time and blow out of horizontal dimensions occurs. Further very deep trenches are difficult to fill.
SUMMARY OF THE INVENTION
A first aspect of the present invention is a method of increasing the capacitance of a trench capacitor by increasing sidewall area, comprising: forming a trench in a silicon substrate, the trench having a sidewall; forming islands on the sidewall of the trench; and etching pits into the sidewall using the islands as a mask.
A second aspect of the present invention is a method of fabricating a trench capacitor, comprising: forming a trench in a silicon substrate, the trench having a sidewall; forming islands on the sidewall of the trench; etching pits into the sidewall using the islands as a mask; forming a node insulator on the pits and the sidewall; and filling the trench with a trench conductor.
A third aspect of the present invention is a trench capacitor, comprising: a trench in a silicon substrate, the trench having a sidewall; pits etched into the sidewall; a node insulator on the pits and the sidewall; and a trench conductor filling the trench.
A fourth aspect of the present invention is a dynamic random access memory cell, comprising: a FET comprising: a first and second source/drain region formed in a silicon substrate; a channel region between the first and second source/drain regions; a gate dielectric formed over the channel region; a wordline formed over the gate dielectric; and a bitline electrically connected to the first source/drain; a trench capacitor comprising: a trench in the silicon substrate, the trench having a sidewall; pits etched into the sidewall; a node insulator on the pits and the sidewall; and a trench conductor filling the trench.; and the second source/drain electrically connected to the trench conductor.
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Furukawa Toshiharu
Hakey Mark C.
Holmes Steven J.
Ma William H.
Chadurjian Mark F.
International Business Machines - Corporation
Schmeiser Olsen & Watts
Thomas Toniae M.
Zarabian Amir
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